Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16006	0	0
TransStop_A	2147483647	8214	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16006	0	0
T1	3858216	16	0	0
T2	761860	0	0	0
T3	0	50	0	0
T4	560332	0	0	0
T6	37876	35	0	0
T7	9884	4	0	0
T10	0	186	0	0
T11	0	408	0	0
T17	17364	0	0	0
T18	25236	29	0	0
T24	15468	0	0	0
T25	6488	0	0	0
T26	6548	0	0	0
T41	0	39	0	0
T110	0	4	0	0
T111	0	28	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8214	0	0
T1	3858216	16	0	0
T2	761860	0	0	0
T3	0	27	0	0
T4	560332	0	0	0
T6	37876	21	0	0
T7	9884	4	0	0
T10	0	105	0	0
T11	0	198	0	0
T17	17364	0	0	0
T18	25236	5	0	0
T24	15468	0	0	0
T25	6488	0	0	0
T26	6548	0	0	0
T41	0	18	0	0
T110	0	4	0	0
T111	0	19	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	553902806	3979	0	0
TransStop_A	553902806	2054	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902806	3979	0	0
T1	964554	4	0	0
T2	190465	0	0	0
T3	0	11	0	0
T4	140083	0	0	0
T6	9469	8	0	0
T7	2471	1	0	0
T10	0	43	0	0
T11	0	104	0	0
T17	4341	0	0	0
T18	6309	8	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1637	0	0	0
T41	0	14	0	0
T110	0	1	0	0
T111	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902806	2054	0	0
T1	964554	4	0	0
T2	190465	0	0	0
T3	0	7	0	0
T4	140083	0	0	0
T6	9469	4	0	0
T7	2471	1	0	0
T10	0	27	0	0
T11	0	53	0	0
T17	4341	0	0	0
T18	6309	1	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1637	0	0	0
T41	0	8	0	0
T110	0	1	0	0
T111	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	553902806	4017	0	0
TransStop_A	553902806	2034	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902806	4017	0	0
T1	964554	4	0	0
T2	190465	0	0	0
T3	0	15	0	0
T4	140083	0	0	0
T6	9469	10	0	0
T7	2471	1	0	0
T10	0	45	0	0
T11	0	107	0	0
T17	4341	0	0	0
T18	6309	8	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1637	0	0	0
T41	0	10	0	0
T110	0	1	0	0
T111	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902806	2034	0	0
T1	964554	4	0	0
T2	190465	0	0	0
T3	0	7	0	0
T4	140083	0	0	0
T6	9469	7	0	0
T7	2471	1	0	0
T10	0	27	0	0
T11	0	46	0	0
T17	4341	0	0	0
T18	6309	1	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1637	0	0	0
T41	0	5	0	0
T110	0	1	0	0
T111	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	553902806	4048	0	0
TransStop_A	553902806	2108	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902806	4048	0	0
T1	964554	4	0	0
T2	190465	0	0	0
T3	0	13	0	0
T4	140083	0	0	0
T6	9469	9	0	0
T7	2471	1	0	0
T10	0	44	0	0
T11	0	104	0	0
T17	4341	0	0	0
T18	6309	7	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1637	0	0	0
T41	0	7	0	0
T110	0	1	0	0
T111	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902806	2108	0	0
T1	964554	4	0	0
T2	190465	0	0	0
T3	0	8	0	0
T4	140083	0	0	0
T6	9469	4	0	0
T7	2471	1	0	0
T10	0	20	0	0
T11	0	55	0	0
T17	4341	0	0	0
T18	6309	2	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1637	0	0	0
T41	0	3	0	0
T110	0	1	0	0
T111	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	553902806	3962	0	0
TransStop_A	553902806	2018	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902806	3962	0	0
T1	964554	4	0	0
T2	190465	0	0	0
T3	0	11	0	0
T4	140083	0	0	0
T6	9469	8	0	0
T7	2471	1	0	0
T10	0	54	0	0
T11	0	93	0	0
T17	4341	0	0	0
T18	6309	6	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1637	0	0	0
T41	0	8	0	0
T110	0	1	0	0
T111	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902806	2018	0	0
T1	964554	4	0	0
T2	190465	0	0	0
T3	0	5	0	0
T4	140083	0	0	0
T6	9469	6	0	0
T7	2471	1	0	0
T10	0	31	0	0
T11	0	44	0	0
T17	4341	0	0	0
T18	6309	1	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1637	0	0	0
T41	0	2	0	0
T110	0	1	0	0
T111	0	5	0	0