Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10CoveredT5,T24,T26 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T24,T26
11CoveredT5,T24,T26 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T24,T26
10CoveredT5,T6,T7
11CoveredT5,T6,T7
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 649007840 649005428 0 0
selKnown1 1562937708 1562935296 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 649007840 649005428 0 0
T1 1013060 1013057 0 0
T2 228485 228482 0 0
T4 97206 97203 0 0
T5 9508 9505 0 0
T6 11313 11310 0 0
T7 2815 2812 0 0
T17 5396 5393 0 0
T24 4757 4754 0 0
T25 1848 1845 0 0
T26 2866 2863 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562937708 1562935296 0 0
T1 2432241 2432238 0 0
T2 548523 548520 0 0
T4 403422 403419 0 0
T5 20796 20793 0 0
T6 27267 27264 0 0
T7 7116 7113 0 0
T17 12504 12501 0 0
T24 11136 11133 0 0
T25 4671 4668 0 0
T26 4713 4710 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 259742289 259741485 0 0
selKnown1 520979236 520978432 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 259742289 259741485 0 0
T1 405481 405480 0 0
T2 91394 91393 0 0
T4 38883 38882 0 0
T5 4047 4046 0 0
T6 4525 4524 0 0
T7 1126 1125 0 0
T17 2235 2234 0 0
T24 1975 1974 0 0
T25 739 738 0 0
T26 1409 1408 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 520979236 520978432 0 0
T1 810747 810746 0 0
T2 182841 182840 0 0
T4 134474 134473 0 0
T5 6932 6931 0 0
T6 9089 9088 0 0
T7 2372 2371 0 0
T17 4168 4167 0 0
T24 3712 3711 0 0
T25 1557 1556 0 0
T26 1571 1570 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10CoveredT5,T24,T26 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T24,T26
11CoveredT5,T24,T26 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T24,T26
10CoveredT5,T6,T7
11CoveredT5,T6,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 259395051 259394247 0 0
selKnown1 520979236 520978432 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 259395051 259394247 0 0
T1 404844 404843 0 0
T2 91394 91393 0 0
T4 38883 38882 0 0
T5 3440 3439 0 0
T6 4525 4524 0 0
T7 1126 1125 0 0
T17 2044 2043 0 0
T24 1796 1795 0 0
T25 739 738 0 0
T26 753 752 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 520979236 520978432 0 0
T1 810747 810746 0 0
T2 182841 182840 0 0
T4 134474 134473 0 0
T5 6932 6931 0 0
T6 9089 9088 0 0
T7 2372 2371 0 0
T17 4168 4167 0 0
T24 3712 3711 0 0
T25 1557 1556 0 0
T26 1571 1570 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 129870500 129869696 0 0
selKnown1 520979236 520978432 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 129870500 129869696 0 0
T1 202735 202734 0 0
T2 45697 45696 0 0
T4 19440 19439 0 0
T5 2021 2020 0 0
T6 2263 2262 0 0
T7 563 562 0 0
T17 1117 1116 0 0
T24 986 985 0 0
T25 370 369 0 0
T26 704 703 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 520979236 520978432 0 0
T1 810747 810746 0 0
T2 182841 182840 0 0
T4 134474 134473 0 0
T5 6932 6931 0 0
T6 9089 9088 0 0
T7 2372 2371 0 0
T17 4168 4167 0 0
T24 3712 3711 0 0
T25 1557 1556 0 0
T26 1571 1570 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%