Module Definition
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Module Instance : tb.dut.u_io_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 100.00 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.78 100.00 95.56 100.00 100.00 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_calib_rdy_sync 100.00 100.00 100.00 100.00
u_err_sync 93.75 100.00 75.00 100.00 100.00
u_meas 94.29 100.00 100.00 100.00 100.00 71.43
u_timeout_err_sync 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 100.00 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.78 100.00 95.56 100.00 100.00 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_calib_rdy_sync 100.00 100.00 100.00 100.00
u_err_sync 93.75 100.00 75.00 100.00 100.00
u_meas 94.29 100.00 100.00 100.00 100.00 71.43
u_timeout_err_sync 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 100.00 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.78 100.00 95.56 100.00 100.00 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_calib_rdy_sync 100.00 100.00 100.00 100.00
u_err_sync 93.75 100.00 75.00 100.00 100.00
u_meas 94.29 100.00 100.00 100.00 100.00 71.43
u_timeout_err_sync 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 100.00 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.78 100.00 95.56 100.00 100.00 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_calib_rdy_sync 100.00 100.00 100.00 100.00
u_err_sync 93.75 100.00 75.00 100.00 100.00
u_meas 94.29 100.00 100.00 100.00 100.00 71.43
u_timeout_err_sync 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 100.00 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.78 100.00 95.56 100.00 100.00 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_calib_rdy_sync 100.00 100.00 100.00 100.00
u_err_sync 93.75 100.00 75.00 100.00 100.00
u_meas 94.29 100.00 100.00 100.00 100.00 71.43
u_timeout_err_sync 100.00 100.00 100.00 100.00

Line Coverage for Module : clkmgr_meas_chk
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS7655100.00
ALWAYS9366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
76 1 1
77 1 1
81 1 1
83 1 1
84 1 1
MISSING_ELSE
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
MISSING_ELSE


Cond Coverage for Module : clkmgr_meas_chk
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Module : clkmgr_meas_chk
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 81 2 2 100.00
IF 93 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 81 if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T7


LineNo. Expression -1-: 93 if ((!rst_src_ni)) -2-: 95 if ((src_fast_err || src_slow_err)) -3-: 97 if ((src_err_req && src_err_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_io_meas
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS7655100.00
ALWAYS9366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
76 1 1
77 1 1
81 1 1
83 1 1
84 1 1
MISSING_ELSE
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_meas
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_meas
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 81 2 2 100.00
IF 93 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 81 if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T7


LineNo. Expression -1-: 93 if ((!rst_src_ni)) -2-: 95 if ((src_fast_err || src_slow_err)) -3-: 97 if ((src_err_req && src_err_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_io_div2_meas
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS7655100.00
ALWAYS9366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
76 1 1
77 1 1
81 1 1
83 1 1
84 1 1
MISSING_ELSE
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div2_meas
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div2_meas
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 81 2 2 100.00
IF 93 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 81 if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T7


LineNo. Expression -1-: 93 if ((!rst_src_ni)) -2-: 95 if ((src_fast_err || src_slow_err)) -3-: 97 if ((src_err_req && src_err_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_io_div4_meas
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS7655100.00
ALWAYS9366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
76 1 1
77 1 1
81 1 1
83 1 1
84 1 1
MISSING_ELSE
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div4_meas
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT2,T10,T11
10CoveredT1,T3,T10

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div4_meas
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 81 2 2 100.00
IF 93 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 81 if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T7


LineNo. Expression -1-: 93 if ((!rst_src_ni)) -2-: 95 if ((src_fast_err || src_slow_err)) -3-: 97 if ((src_err_req && src_err_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_main_meas
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS7655100.00
ALWAYS9366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
76 1 1
77 1 1
81 1 1
83 1 1
84 1 1
MISSING_ELSE
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_main_meas
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_main_meas
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 81 2 2 100.00
IF 93 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 81 if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T7


LineNo. Expression -1-: 93 if ((!rst_src_ni)) -2-: 95 if ((src_fast_err || src_slow_err)) -3-: 97 if ((src_err_req && src_err_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_usb_meas
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS7655100.00
ALWAYS9366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
76 1 1
77 1 1
81 1 1
83 1 1
84 1 1
MISSING_ELSE
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
98 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_usb_meas
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T3,T10
10CoveredT1,T2,T3

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_usb_meas
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 81 2 2 100.00
IF 93 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 81 if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T7


LineNo. Expression -1-: 93 if ((!rst_src_ni)) -2-: 95 if ((src_fast_err || src_slow_err)) -3-: 97 if ((src_err_req && src_err_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%