Module Definition
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Module : clkmgr_lost_calib_regwen_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RegwenOff_A 152872116 18210306 0 56


RegwenOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 152872116 18210306 0 56
T1 490275 20508 0 0
T2 78091 16185 0 1
T3 0 44641 0 1
T4 23813 0 0 0
T10 0 110818 0 0
T11 0 202382 0 0
T12 0 8018 0 0
T13 0 10487 0 1
T14 0 5346 0 1
T15 0 85192 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 0 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T27 0 1415 0 1
T66 0 0 0 1
T112 0 0 0 1
T113 0 0 0 1
T114 0 0 0 1
T115 0 0 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%