Unified Coverage Report :: Module :: clkmgr_extclk_sva_if

Module : clkmgr_extclk_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_extclk_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_extclk_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_extclk_sva_if

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	34	1	1	100.00
ALWAYS	49	1	1	100.00
ALWAYS	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
49	1	1
66	1	1

---

Cond Coverage for Module : clkmgr_extclk_sva_if

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (lc_clk_byp_req_i == On)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T24,T26
1	Covered	T5,T24,T26

 LINE       49
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T26
1	0	Covered	T5,T26,T1
1	1	Covered	T5,T24,T26

 LINE       49
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T5,T24,T26
1	Covered	T5,T24,T26

 LINE       49
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T24,T26
1	Covered	T5,T24,T26

 LINE       66
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (extclk_ctrl_hi_speed_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    -------------------2-------------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T24,T1
1	0	1	Covered	T5,T24,T26
1	1	0	Covered	T5,T1,T17
1	1	1	Covered	T5,T24,T26

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T5,T24,T26
1	Covered	T5,T24,T26

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_hi_speed_sel == MuBi4True)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T5,T24,T26
1	Covered	T5,T24,T26

 LINE       66
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T24,T26
1	Covered	T5,T24,T26

---

Assert Coverage for Module : clkmgr_extclk_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFall_A	152872116	4247	0	0
AllClkBypReqRise_A	152872116	4247	0	0
HiSpeedSelFall_A	152872116	2587	0	0
HiSpeedSelRise_A	152872116	2587	0	0
IoClkBypReqFall_A	152872116	5292	0	0
IoClkBypReqRise_A	152872116	5292	0	0

AllClkBypReqFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	4247	0	0
T1	490275	21	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	12	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	5	0	0
T19	0	1	0	0
T20	0	3	0	0
T22	0	7	0	0
T23	0	8	0	0
T24	1895	6	0	0
T25	1477	0	0	0
T26	1636	2	0	0
T62	0	1	0	0

AllClkBypReqRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	4247	0	0
T1	490275	21	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	12	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	5	0	0
T19	0	1	0	0
T20	0	3	0	0
T22	0	7	0	0
T23	0	8	0	0
T24	1895	6	0	0
T25	1477	0	0	0
T26	1636	2	0	0
T62	0	1	0	0

HiSpeedSelFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	2587	0	0
T1	490275	10	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	5	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	2	0	0
T19	0	1	0	0
T20	0	3	0	0
T22	0	5	0	0
T23	0	6	0	0
T24	1895	5	0	0
T25	1477	0	0	0
T26	1636	1	0	0
T62	0	1	0	0

HiSpeedSelRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	2587	0	0
T1	490275	10	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	5	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	2	0	0
T19	0	1	0	0
T20	0	3	0	0
T22	0	5	0	0
T23	0	6	0	0
T24	1895	5	0	0
T25	1477	0	0	0
T26	1636	1	0	0
T62	0	1	0	0

IoClkBypReqFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	5292	0	0
T1	490275	25	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	13	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	9	0	0
T19	0	6	0	0
T22	0	1	0	0
T24	1895	6	0	0
T25	1477	0	0	0
T26	1636	1	0	0
T62	0	6	0	0
T93	0	7	0	0
T108	0	12	0	0

IoClkBypReqRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	5292	0	0
T1	490275	25	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	13	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	9	0	0
T19	0	6	0	0
T22	0	1	0	0
T24	1895	6	0	0
T25	1477	0	0	0
T26	1636	1	0	0
T62	0	6	0	0
T93	0	7	0	0
T108	0	12	0	0