Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div2_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div4_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_main_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_usb_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_div2_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_div2_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_div4_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_div4_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_main_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_main_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_usb_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_usb_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 966248 0 0
SrcPulseCheck_M 2147483647 961726 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 966248 0 0
T1 3684753 3128 0 0
T2 771276 392 0 0
T3 0 2556 0 0
T4 434458 180 0 0
T10 0 8859 0 0
T11 0 13024 0 0
T12 0 1065 0 0
T13 0 456 0 0
T17 17937 0 0 0
T18 25307 0 0 0
T19 10057 0 0 0
T20 23165 0 0 0
T21 122644 40 0 0
T22 60961 0 0 0
T23 16431 0 0 0
T27 0 440 0 0
T29 0 190 0 0
T30 0 352 0 0
T47 5127 0 0 0
T48 17804 2 0 0
T52 13954 1 0 0
T53 15302 3 0 0
T55 19384 2 0 0
T116 28512 1 0 0
T117 11308 2 0 0
T118 30938 1 0 0
T119 9822 1 0 0
T120 6760 1 0 0
T121 11865 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 961726 0 0
T1 1399567 3128 0 0
T2 249160 392 0 0
T3 0 2556 0 0
T4 87705 180 0 0
T10 0 8862 0 0
T11 0 12378 0 0
T12 0 1065 0 0
T13 0 456 0 0
T17 6659 0 0 0
T18 9681 0 0 0
T19 5985 0 0 0
T20 7391 0 0 0
T21 71913 40 0 0
T22 15109 0 0 0
T23 6956 0 0 0
T27 0 440 0 0
T29 0 190 0 0
T30 0 352 0 0
T47 13607 0 0 0
T48 9184 2 0 0
T52 6012 1 0 0
T53 7964 3 0 0
T55 9304 2 0 0
T116 12178 1 0 0
T117 4631 2 0 0
T118 14566 1 0 0
T119 65878 1 0 0
T120 2916 1 0 0
T121 4676 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 523041180 25639 0 0
SrcPulseCheck_M 153726728 25639 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 523041180 25639 0 0
T1 810747 164 0 0
T2 182841 32 0 0
T3 0 152 0 0
T4 134474 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 4168 0 0 0
T18 6056 0 0 0
T19 2083 0 0 0
T20 5678 0 0 0
T21 30866 8 0 0
T22 15490 0 0 0
T23 3771 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 25639 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 8 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 523041180 31102 0 0
SrcPulseCheck_M 153726728 31117 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 523041180 31102 0 0
T1 810747 164 0 0
T2 182841 32 0 0
T3 0 152 0 0
T4 134474 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 4168 0 0 0
T18 6056 0 0 0
T19 2083 0 0 0
T20 5678 0 0 0
T21 30866 16 0 0
T22 15490 0 0 0
T23 3771 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31117 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 31091 0 0
SrcPulseCheck_M 523041180 31107 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31091 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 523041180 31107 0 0
T1 810747 164 0 0
T2 182841 32 0 0
T3 0 152 0 0
T4 134474 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 4168 0 0 0
T18 6056 0 0 0
T19 2083 0 0 0
T20 5678 0 0 0
T21 30866 16 0 0
T22 15490 0 0 0
T23 3771 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 260729162 25639 0 0
SrcPulseCheck_M 153726728 25639 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 260729162 25639 0 0
T1 405481 164 0 0
T2 91394 32 0 0
T3 0 152 0 0
T4 38883 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 2235 0 0 0
T18 2995 0 0 0
T19 1039 0 0 0
T20 2901 0 0 0
T21 7941 8 0 0
T22 8013 0 0 0
T23 1934 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 25639 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 8 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 260729162 31175 0 0
SrcPulseCheck_M 153726728 31209 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 260729162 31175 0 0
T1 405481 164 0 0
T2 91394 32 0 0
T3 0 152 0 0
T4 38883 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 2235 0 0 0
T18 2995 0 0 0
T19 1039 0 0 0
T20 2901 0 0 0
T21 7941 16 0 0
T22 8013 0 0 0
T23 1934 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31209 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 31169 0 0
SrcPulseCheck_M 260729162 31180 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31169 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 260729162 31180 0 0
T1 405481 164 0 0
T2 91394 32 0 0
T3 0 152 0 0
T4 38883 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 2235 0 0 0
T18 2995 0 0 0
T19 1039 0 0 0
T20 2901 0 0 0
T21 7941 16 0 0
T22 8013 0 0 0
T23 1934 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 130363936 25639 0 0
SrcPulseCheck_M 153726728 25639 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130363936 25639 0 0
T1 202735 164 0 0
T2 45697 32 0 0
T3 0 152 0 0
T4 19440 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 1117 0 0 0
T18 1497 0 0 0
T19 519 0 0 0
T20 1450 0 0 0
T21 3970 8 0 0
T22 4006 0 0 0
T23 966 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 25639 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 8 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 130363936 31019 0 0
SrcPulseCheck_M 153726728 31047 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130363936 31019 0 0
T1 202735 164 0 0
T2 45697 32 0 0
T3 0 152 0 0
T4 19440 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1117 0 0 0
T18 1497 0 0 0
T19 519 0 0 0
T20 1450 0 0 0
T21 3970 16 0 0
T22 4006 0 0 0
T23 966 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31047 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 31018 0 0
SrcPulseCheck_M 130363936 31021 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31018 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 130363936 31021 0 0
T1 202735 164 0 0
T2 45697 32 0 0
T3 0 152 0 0
T4 19440 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1117 0 0 0
T18 1497 0 0 0
T19 519 0 0 0
T20 1450 0 0 0
T21 3970 16 0 0
T22 4006 0 0 0
T23 966 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 556050311 25639 0 0
SrcPulseCheck_M 153726728 25639 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556050311 25639 0 0
T1 964553 164 0 0
T2 190465 32 0 0
T3 0 152 0 0
T4 140082 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 4341 0 0 0
T18 6308 0 0 0
T19 2169 0 0 0
T20 5915 0 0 0
T21 32153 8 0 0
T22 16136 0 0 0
T23 3929 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 25639 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 8 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 556050311 31119 0 0
SrcPulseCheck_M 153726728 31135 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556050311 31119 0 0
T1 964553 164 0 0
T2 190465 32 0 0
T3 0 152 0 0
T4 140082 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 4341 0 0 0
T18 6308 0 0 0
T19 2169 0 0 0
T20 5915 0 0 0
T21 32153 16 0 0
T22 16136 0 0 0
T23 3929 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31135 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 31103 0 0
SrcPulseCheck_M 556050311 31122 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31103 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 556050311 31122 0 0
T1 964553 164 0 0
T2 190465 32 0 0
T3 0 152 0 0
T4 140082 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 4341 0 0 0
T18 6308 0 0 0
T19 2169 0 0 0
T20 5915 0 0 0
T21 32153 16 0 0
T22 16136 0 0 0
T23 3929 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 266969388 25185 0 0
SrcPulseCheck_M 153726728 25639 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266969388 25185 0 0
T1 465873 164 0 0
T2 91424 32 0 0
T3 0 152 0 0
T4 67240 18 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 2084 0 0 0
T18 3028 0 0 0
T19 1041 0 0 0
T20 2839 0 0 0
T21 15434 4 0 0
T22 7745 0 0 0
T23 1885 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 25639 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 36 0 0
T10 0 446 0 0
T11 0 715 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 8 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 266969388 30957 0 0
SrcPulseCheck_M 153726728 31114 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266969388 30957 0 0
T1 465873 164 0 0
T2 91424 32 0 0
T3 0 152 0 0
T4 67240 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 2084 0 0 0
T18 3028 0 0 0
T19 1041 0 0 0
T20 2839 0 0 0
T21 15434 12 0 0
T22 7745 0 0 0
T23 1885 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 31114 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 16 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T4,T2
10CoveredT1,T4,T2
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 30802 0 0
SrcPulseCheck_M 266969388 30989 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 30802 0 0
T1 490275 164 0 0
T2 78091 32 0 0
T3 0 152 0 0
T4 23813 54 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 1606 0 0 0
T18 2461 0 0 0
T19 2169 0 0 0
T20 1419 0 0 0
T21 31832 12 0 0
T22 1290 0 0 0
T23 1963 0 0 0
T29 0 6 0 0
T30 0 16 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 266969388 30989 0 0
T1 465873 164 0 0
T2 91424 32 0 0
T3 0 152 0 0
T4 67240 72 0 0
T10 0 458 0 0
T11 0 726 0 0
T12 0 62 0 0
T17 2084 0 0 0
T18 3028 0 0 0
T19 1041 0 0 0
T20 2839 0 0 0
T21 15434 12 0 0
T22 7745 0 0 0
T23 1885 0 0 0
T29 0 6 0 0
T30 0 16 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T50,T51
10CoveredT47,T50,T51
11CoveredT47,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T50,T51
10CoveredT47,T122
11CoveredT47,T50,T51

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 26 0 0
SrcPulseCheck_M 523041180 26 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 26 0 0
T47 5127 2 0 0
T50 3589 1 0 0
T51 7082 1 0 0
T53 7651 2 0 0
T55 9692 1 0 0
T116 14256 1 0 0
T117 11308 1 0 0
T118 15469 1 0 0
T121 11865 1 0 0
T123 1920 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 523041180 26 0 0
T47 28956 2 0 0
T50 31325 1 0 0
T51 11522 1 0 0
T53 9416 2 0 0
T55 11345 1 0 0
T116 14256 1 0 0
T117 10855 1 0 0
T118 16684 1 0 0
T121 11390 1 0 0
T123 18435 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT50,T51,T53
10CoveredT50,T51,T53
11CoveredT124,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT50,T51,T53
10CoveredT124,T122
11CoveredT50,T51,T53

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 23 0 0
SrcPulseCheck_M 523041180 23 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 23 0 0
T50 3589 1 0 0
T51 7082 1 0 0
T53 7651 2 0 0
T117 11308 1 0 0
T121 11865 1 0 0
T123 1920 1 0 0
T124 5475 4 0 0
T125 6638 1 0 0
T126 5283 1 0 0
T127 5534 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 523041180 23 0 0
T50 31325 1 0 0
T51 11522 1 0 0
T53 9416 2 0 0
T117 10855 1 0 0
T121 11390 1 0 0
T123 18435 1 0 0
T124 21024 4 0 0
T125 13005 1 0 0
T126 5698 1 0 0
T127 21251 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT48,T55,T52
10CoveredT48,T55,T52
11CoveredT48,T53,T117

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT48,T55,T52
10CoveredT48,T53,T117
11CoveredT48,T55,T52

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 30 0 0
SrcPulseCheck_M 260729162 30 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 30 0 0
T48 8902 2 0 0
T52 6977 1 0 0
T53 7651 3 0 0
T55 9692 2 0 0
T116 14256 1 0 0
T117 11308 2 0 0
T118 15469 1 0 0
T119 4911 1 0 0
T120 6760 1 0 0
T121 11865 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 260729162 30 0 0
T48 4592 2 0 0
T52 3006 1 0 0
T53 3982 3 0 0
T55 4652 2 0 0
T116 6089 1 0 0
T117 4631 2 0 0
T118 7283 1 0 0
T119 32939 1 0 0
T120 2916 1 0 0
T121 4676 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T48,T55
10CoveredT47,T48,T55
11CoveredT55,T52,T53

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T48,T55
10CoveredT55,T52,T53
11CoveredT47,T48,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 37 0 0
SrcPulseCheck_M 260729162 37 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 37 0 0
T47 5127 1 0 0
T48 8902 1 0 0
T52 6977 2 0 0
T53 7651 2 0 0
T55 9692 3 0 0
T116 14256 2 0 0
T118 15469 2 0 0
T119 4911 1 0 0
T123 1920 2 0 0
T128 3636 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 260729162 37 0 0
T47 13607 1 0 0
T48 4592 1 0 0
T52 3006 2 0 0
T53 3982 2 0 0
T55 4652 3 0 0
T116 6089 2 0 0
T118 7283 2 0 0
T119 32939 1 0 0
T123 8912 2 0 0
T128 28508 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT48,T50,T51
10CoveredT48,T50,T51
11CoveredT123,T129,T130

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT48,T50,T51
10CoveredT123,T129,T130
11CoveredT48,T50,T51

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 32 0 0
SrcPulseCheck_M 130363936 32 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 32 0 0
T48 8902 1 0 0
T50 3589 1 0 0
T51 7082 1 0 0
T52 6977 1 0 0
T116 14256 2 0 0
T117 11308 2 0 0
T119 4911 2 0 0
T121 11865 1 0 0
T123 1920 3 0 0
T128 3636 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 130363936 32 0 0
T48 2294 1 0 0
T50 7591 1 0 0
T51 2571 1 0 0
T52 1505 1 0 0
T116 3045 2 0 0
T117 2315 2 0 0
T119 16469 2 0 0
T121 2339 1 0 0
T123 4457 3 0 0
T128 14254 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT48,T50,T51
10CoveredT48,T50,T51
11CoveredT123,T124,T131

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT48,T50,T51
10CoveredT123,T124,T131
11CoveredT48,T50,T51

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 33 0 0
SrcPulseCheck_M 130363936 33 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 33 0 0
T48 8902 1 0 0
T50 3589 1 0 0
T51 7082 1 0 0
T52 6977 1 0 0
T116 14256 2 0 0
T119 4911 1 0 0
T120 6760 2 0 0
T121 11865 1 0 0
T123 1920 3 0 0
T128 3636 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 130363936 33 0 0
T48 2294 1 0 0
T50 7591 1 0 0
T51 2571 1 0 0
T52 1505 1 0 0
T116 3045 2 0 0
T119 16469 1 0 0
T120 1460 2 0 0
T121 2339 1 0 0
T123 4457 3 0 0
T128 14254 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT50,T55,T53
10CoveredT50,T55,T53
11CoveredT123,T124,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT50,T55,T53
10CoveredT123,T124,T132
11CoveredT50,T55,T53

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 32 0 0
SrcPulseCheck_M 556050311 32 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 32 0 0
T50 3589 1 0 0
T53 7651 1 0 0
T55 9692 1 0 0
T117 11308 1 0 0
T118 15469 2 0 0
T119 4911 1 0 0
T120 6760 2 0 0
T121 11865 1 0 0
T123 1920 2 0 0
T124 5475 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 556050311 32 0 0
T50 32632 1 0 0
T53 9809 1 0 0
T55 11819 1 0 0
T117 11308 1 0 0
T118 17380 2 0 0
T119 70171 1 0 0
T120 6828 2 0 0
T121 11865 1 0 0
T123 19205 2 0 0
T124 21901 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T50,T55
10CoveredT47,T50,T55
11CoveredT123,T124,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T50,T55
10CoveredT123,T124,T132
11CoveredT47,T50,T55

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 34 0 0
SrcPulseCheck_M 556050311 34 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 34 0 0
T47 5127 2 0 0
T50 3589 1 0 0
T53 7651 1 0 0
T55 9692 1 0 0
T117 11308 1 0 0
T118 15469 1 0 0
T119 4911 1 0 0
T120 6760 2 0 0
T121 11865 1 0 0
T123 1920 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 556050311 34 0 0
T47 30164 2 0 0
T50 32632 1 0 0
T53 9809 1 0 0
T55 11819 1 0 0
T117 11308 1 0 0
T118 17380 1 0 0
T119 70171 1 0 0
T120 6828 2 0 0
T121 11865 1 0 0
T123 19205 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T50,T55
10CoveredT47,T50,T55
11CoveredT118,T126,T130

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T50,T55
10CoveredT118,T126,T130
11CoveredT47,T50,T55

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 32 0 0
SrcPulseCheck_M 266969388 32 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 32 0 0
T47 5127 2 0 0
T50 3589 1 0 0
T53 7651 3 0 0
T55 9692 1 0 0
T116 14256 1 0 0
T118 15469 3 0 0
T120 6760 1 0 0
T121 11865 1 0 0
T124 5475 1 0 0
T128 3636 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 266969388 32 0 0
T47 14478 2 0 0
T50 15663 1 0 0
T53 4709 3 0 0
T55 5672 1 0 0
T116 7129 1 0 0
T118 8342 3 0 0
T120 3278 1 0 0
T121 5695 1 0 0
T124 10513 1 0 0
T128 29095 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T50,T51
10CoveredT47,T50,T51
11CoveredT118,T126,T133

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT47,T50,T51
10CoveredT118,T126,T133
11CoveredT47,T50,T51

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 153726728 32 0 0
SrcPulseCheck_M 266969388 32 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153726728 32 0 0
T47 5127 2 0 0
T50 3589 1 0 0
T51 7082 1 0 0
T53 7651 2 0 0
T55 9692 2 0 0
T116 14256 1 0 0
T118 15469 4 0 0
T119 4911 1 0 0
T121 11865 1 0 0
T128 3636 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 266969388 32 0 0
T47 14478 2 0 0
T50 15663 1 0 0
T51 5762 1 0 0
T53 4709 2 0 0
T55 5672 2 0 0
T116 7129 1 0 0
T118 8342 4 0 0
T119 33682 1 0 0
T121 5695 1 0 0
T128 29095 1 0 0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 520979236 99380 0 0
SrcPulseCheck_M 21287939 98258 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 520979236 99380 0 0
T1 810747 599 0 0
T2 182841 74 0 0
T3 0 495 0 0
T4 134474 0 0 0
T10 0 1765 0 0
T11 0 2553 0 0
T12 0 243 0 0
T13 0 114 0 0
T17 4168 0 0 0
T18 6056 0 0 0
T19 2083 0 0 0
T20 5678 0 0 0
T21 30866 0 0 0
T22 15490 0 0 0
T23 3771 0 0 0
T27 0 98 0 0
T29 0 46 0 0
T30 0 58 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 21287939 98258 0 0
T1 3324 599 0 0
T2 396 74 0 0
T3 0 495 0 0
T4 299 0 0 0
T10 0 1766 0 0
T11 0 2553 0 0
T12 0 243 0 0
T13 0 114 0 0
T17 303 0 0 0
T18 441 0 0 0
T19 152 0 0 0
T20 413 0 0 0
T21 77 0 0 0
T22 1129 0 0 0
T23 274 0 0 0
T27 0 98 0 0
T29 0 46 0 0
T30 0 58 0 0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 259742289 98415 0 0
SrcPulseCheck_M 21287939 97294 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 259742289 98415 0 0
T1 405481 599 0 0
T2 91394 74 0 0
T3 0 495 0 0
T4 38883 0 0 0
T10 0 1765 0 0
T11 0 2553 0 0
T12 0 227 0 0
T13 0 114 0 0
T17 2235 0 0 0
T18 2995 0 0 0
T19 1039 0 0 0
T20 2901 0 0 0
T21 7941 0 0 0
T22 8013 0 0 0
T23 1934 0 0 0
T27 0 98 0 0
T29 0 46 0 0
T30 0 58 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 21287939 97294 0 0
T1 3324 599 0 0
T2 396 74 0 0
T3 0 495 0 0
T4 299 0 0 0
T10 0 1766 0 0
T11 0 2553 0 0
T12 0 227 0 0
T13 0 114 0 0
T17 303 0 0 0
T18 441 0 0 0
T19 152 0 0 0
T20 413 0 0 0
T21 77 0 0 0
T22 1129 0 0 0
T23 274 0 0 0
T27 0 98 0 0
T29 0 46 0 0
T30 0 58 0 0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 129870500 96787 0 0
SrcPulseCheck_M 21287939 95670 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 129870500 96787 0 0
T1 202735 599 0 0
T2 45697 74 0 0
T3 0 495 0 0
T4 19440 0 0 0
T10 0 1765 0 0
T11 0 2553 0 0
T12 0 212 0 0
T13 0 114 0 0
T17 1117 0 0 0
T18 1497 0 0 0
T19 519 0 0 0
T20 1450 0 0 0
T21 3970 0 0 0
T22 4006 0 0 0
T23 966 0 0 0
T27 0 98 0 0
T29 0 46 0 0
T30 0 58 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 21287939 95670 0 0
T1 3324 599 0 0
T2 396 74 0 0
T3 0 495 0 0
T4 299 0 0 0
T10 0 1766 0 0
T11 0 2553 0 0
T12 0 212 0 0
T13 0 114 0 0
T17 303 0 0 0
T18 441 0 0 0
T19 152 0 0 0
T20 413 0 0 0
T21 77 0 0 0
T22 1129 0 0 0
T23 274 0 0 0
T27 0 98 0 0
T29 0 46 0 0
T30 0 58 0 0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 553902368 117271 0 0
SrcPulseCheck_M 21296129 116077 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 553902368 117271 0 0
T1 964553 839 0 0
T2 190465 74 0 0
T3 0 615 0 0
T4 140082 0 0 0
T10 0 2202 0 0
T11 0 3198 0 0
T12 0 197 0 0
T13 0 114 0 0
T17 4341 0 0 0
T18 6308 0 0 0
T19 2169 0 0 0
T20 5915 0 0 0
T21 32153 0 0 0
T22 16136 0 0 0
T23 3929 0 0 0
T27 0 146 0 0
T29 0 34 0 0
T30 0 130 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 21296129 116077 0 0
T1 3564 839 0 0
T2 396 74 0 0
T3 0 615 0 0
T4 299 0 0 0
T10 0 2202 0 0
T11 0 2552 0 0
T12 0 197 0 0
T13 0 114 0 0
T17 303 0 0 0
T18 441 0 0 0
T19 152 0 0 0
T20 413 0 0 0
T21 77 0 0 0
T22 1129 0 0 0
T23 274 0 0 0
T27 0 146 0 0
T29 0 34 0 0
T30 0 130 0 0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T29
10CoveredT1,T2,T29
11CoveredT1,T2,T29

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 265938401 115788 0 0
SrcPulseCheck_M 21286382 114880 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 265938401 115788 0 0
T1 465873 851 0 0
T2 91424 74 0 0
T3 0 627 0 0
T4 67240 0 0 0
T10 0 2215 0 0
T11 0 3081 0 0
T12 0 190 0 0
T13 0 112 0 0
T17 2084 0 0 0
T18 3028 0 0 0
T19 1041 0 0 0
T20 2839 0 0 0
T21 15434 0 0 0
T22 7745 0 0 0
T23 1885 0 0 0
T27 0 110 0 0
T29 0 22 0 0
T30 0 118 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 21286382 114880 0 0
T1 3576 851 0 0
T2 396 74 0 0
T3 0 627 0 0
T4 299 0 0 0
T10 0 2132 0 0
T11 0 3081 0 0
T12 0 190 0 0
T13 0 112 0 0
T17 303 0 0 0
T18 441 0 0 0
T19 152 0 0 0
T20 413 0 0 0
T21 77 0 0 0
T22 1129 0 0 0
T23 274 0 0 0
T27 0 110 0 0
T29 0 22 0 0
T30 0 118 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%