Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	153726728	4919506	0	0
clk_enables_rd_A	153726728	30388	0	0
clk_hints_rd_A	153726728	26574	0	0
extclk_ctrl_rd_A	153726728	35175	0	0
extclk_ctrl_regwen_rd_A	153726728	24877	0	0
jitter_enable_rd_A	153726728	38555	0	0
jitter_regwen_rd_A	153726728	28856	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153726728	4919506	0	0
T10	336683	167370	0	0
T11	512687	250001	0	0
T16	0	219277	0	0
T28	0	132250	0	0
T30	95911	0	0	0
T31	1624	0	0	0
T38	1151	0	0	0
T39	1531	0	0	0
T40	1505	0	0	0
T41	3475	0	0	0
T42	2443	0	0	0
T43	1843	0	0	0
T56	0	50264	0	0
T57	0	87185	0	0
T58	0	60942	0	0
T59	0	95863	0	0
T60	0	53955	0	0
T61	0	167590	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153726728	30388	0	0
T1	490275	0	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T7	2397	3	0	0
T17	1606	0	0	0
T18	2461	0	0	0
T19	2169	0	0	0
T24	1895	0	0	0
T25	1477	0	0	0
T26	1636	0	0	0
T27	0	8	0	0
T59	0	3878	0	0
T134	0	19	0	0
T135	0	4	0	0
T136	0	4	0	0
T137	0	1969	0	0
T138	0	3189	0	0
T139	0	12	0	0
T140	0	5	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153726728	26574	0	0
T1	490275	0	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T7	2397	2	0	0
T17	1606	0	0	0
T18	2461	0	0	0
T19	2169	0	0	0
T24	1895	0	0	0
T25	1477	0	0	0
T26	1636	0	0	0
T27	0	11	0	0
T59	0	3238	0	0
T134	0	13	0	0
T135	0	1	0	0
T136	0	3	0	0
T137	0	1803	0	0
T138	0	2858	0	0
T139	0	1	0	0
T141	0	9	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153726728	35175	0	0
T1	490275	0	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	77	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	0	0	0
T19	0	28	0	0
T20	0	31	0	0
T23	0	47	0	0
T24	1895	32	0	0
T25	1477	0	0	0
T26	1636	11	0	0
T27	0	54	0	0
T39	0	23	0	0
T40	0	25	0	0
T108	0	82	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153726728	24877	0	0
T15	434986	0	0	0
T33	712	0	0	0
T59	0	3210	0	0
T77	93455	53	0	0
T78	2174	0	0	0
T79	1424	0	0	0
T80	38437	0	0	0
T107	0	71	0	0
T137	0	1623	0	0
T138	0	2892	0	0
T142	0	4	0	0
T143	0	55	0	0
T144	0	1459	0	0
T145	0	48	0	0
T146	0	32	0	0
T147	885	0	0	0
T148	2171	0	0	0
T149	138205	0	0	0
T150	1300	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153726728	38555	0	0
T1	490275	0	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T7	2397	84	0	0
T17	1606	0	0	0
T18	2461	0	0	0
T19	2169	0	0	0
T24	1895	0	0	0
T25	1477	0	0	0
T26	1636	0	0	0
T27	0	357	0	0
T59	0	4220	0	0
T134	0	360	0	0
T135	0	85	0	0
T136	0	122	0	0
T137	0	2285	0	0
T138	0	4070	0	0
T139	0	226	0	0
T141	0	61	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153726728	28856	0	0
T59	314151	3902	0	0
T115	45784	0	0	0
T137	0	2199	0	0
T138	0	3194	0	0
T144	0	1607	0	0
T151	0	2694	0	0
T152	0	423	0	0
T153	0	3407	0	0
T154	0	1899	0	0
T155	0	4513	0	0
T156	0	1908	0	0
T157	766	0	0	0
T158	2116	0	0	0
T159	1733	0	0	0
T160	109133	0	0	0
T161	1317	0	0	0
T162	1334	0	0	0
T163	1919	0	0	0
T164	1941	0	0	0