Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	458616348	422	0	0
StatusRise_A	458616348	422	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458616348	422	0	0
T15	1304958	0	0	0
T16	1904784	0	0	0
T33	2136	6	0	0
T34	0	12	0	0
T35	0	8	0	0
T79	4272	0	0	0
T80	115311	0	0	0
T147	2655	0	0	0
T148	6513	0	0	0
T149	414615	0	0	0
T150	3900	0	0	0
T165	0	10	0	0
T166	0	16	0	0
T167	0	1	0	0
T168	0	14	0	0
T169	0	3	0	0
T170	0	1	0	0
T171	0	13	0	0
T172	0	6	0	0
T173	0	2	0	0
T174	600105	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458616348	422	0	0
T15	1304958	0	0	0
T16	1904784	0	0	0
T33	2136	6	0	0
T34	0	12	0	0
T35	0	8	0	0
T79	4272	0	0	0
T80	115311	0	0	0
T147	2655	0	0	0
T148	6513	0	0	0
T149	414615	0	0	0
T150	3900	0	0	0
T165	0	10	0	0
T166	0	16	0	0
T167	0	1	0	0
T168	0	14	0	0
T169	0	3	0	0
T170	0	1	0	0
T171	0	13	0	0
T172	0	6	0	0
T173	0	2	0	0
T174	600105	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152872116	146	0	0
StatusRise_A	152872116	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	146	0	0
T15	434986	0	0	0
T16	634928	0	0	0
T33	712	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T79	1424	0	0	0
T80	38437	0	0	0
T147	885	0	0	0
T148	2171	0	0	0
T149	138205	0	0	0
T150	1300	0	0	0
T165	0	4	0	0
T166	0	5	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	5	0	0
T172	0	2	0	0
T174	200035	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	146	0	0
T15	434986	0	0	0
T16	634928	0	0	0
T33	712	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T79	1424	0	0	0
T80	38437	0	0	0
T147	885	0	0	0
T148	2171	0	0	0
T149	138205	0	0	0
T150	1300	0	0	0
T165	0	4	0	0
T166	0	5	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	5	0	0
T172	0	2	0	0
T174	200035	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152872116	133	0	0
StatusRise_A	152872116	133	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	133	0	0
T15	434986	0	0	0
T16	634928	0	0	0
T33	712	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T79	1424	0	0	0
T80	38437	0	0	0
T147	885	0	0	0
T148	2171	0	0	0
T149	138205	0	0	0
T150	1300	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	2	0	0
T174	200035	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	133	0	0
T15	434986	0	0	0
T16	634928	0	0	0
T33	712	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T79	1424	0	0	0
T80	38437	0	0	0
T147	885	0	0	0
T148	2171	0	0	0
T149	138205	0	0	0
T150	1300	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	2	0	0
T174	200035	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152872116	143	0	0
StatusRise_A	152872116	143	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	143	0	0
T15	434986	0	0	0
T16	634928	0	0	0
T33	712	3	0	0
T34	0	4	0	0
T35	0	2	0	0
T79	1424	0	0	0
T80	38437	0	0	0
T147	885	0	0	0
T148	2171	0	0	0
T149	138205	0	0	0
T150	1300	0	0	0
T165	0	3	0	0
T166	0	5	0	0
T168	0	6	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	200035	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	143	0	0
T15	434986	0	0	0
T16	634928	0	0	0
T33	712	3	0	0
T34	0	4	0	0
T35	0	2	0	0
T79	1424	0	0	0
T80	38437	0	0	0
T147	885	0	0	0
T148	2171	0	0	0
T149	138205	0	0	0
T150	1300	0	0	0
T165	0	3	0	0
T166	0	5	0	0
T168	0	6	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	200035	0	0	0