Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50632	0	0
CgEnOn_A	2147483647	41019	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50632	0	0
T1	2383516	131	0	0
T2	510397	3	0	0
T4	332879	57	0	0
T5	13000	3	0	0
T6	25345	11	0	0
T7	6532	5	0	0
T15	874202	0	0	0
T16	1856331	0	0	0
T17	11861	3	0	0
T18	6308	8	0	0
T24	10540	3	0	0
T25	4288	3	0	0
T26	5320	3	0	0
T28	0	5	0	0
T33	11203	5	0	0
T34	0	15	0	0
T35	0	10	0	0
T56	0	5	0	0
T59	0	5	0	0
T79	19907	0	0	0
T80	281104	0	0	0
T147	7804	0	0	0
T148	5134	0	0	0
T149	262292	0	0	0
T150	5940	0	0	0
T165	0	15	0	0
T166	0	30	0	0
T167	0	5	0	0
T168	0	30	0	0
T174	328727	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41019	0	0
T1	1418963	60	0	0
T2	319932	0	0	0
T3	0	33	0	0
T4	192797	0	0	0
T7	2372	0	0	0
T10	0	148	0	0
T11	0	294	0	0
T12	0	47	0	0
T15	874202	0	0	0
T16	1856331	0	0	0
T17	7520	0	0	0
T18	10548	0	0	0
T19	3641	0	0	0
T20	4351	0	0	0
T21	11911	0	0	0
T22	12019	0	0	0
T23	2900	0	0	0
T27	0	62	0	0
T28	0	4	0	0
T33	11203	5	0	0
T34	0	15	0	0
T35	0	10	0	0
T56	0	5	0	0
T59	0	4	0	0
T79	19907	0	0	0
T80	281104	0	0	0
T97	0	6	0	0
T147	7804	0	0	0
T148	5134	0	0	0
T149	262292	0	0	0
T150	5940	0	0	0
T165	0	15	0	0
T166	0	30	0	0
T167	0	5	0	0
T168	0	30	0	0
T169	0	1	0	0
T174	328727	0	0	0
T175	0	26	0	0
T176	0	16	0	0
T177	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	259742289	142	0	0
CgEnOn_A	259742289	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259742289	142	0	0
T15	194173	0	0	0
T16	103129	0	0	0
T28	0	1	0	0
T33	2472	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	4543	0	0	0
T80	62462	0	0	0
T147	1705	0	0	0
T148	1187	0	0	0
T149	58273	0	0	0
T150	1336	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	73042	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259742289	142	0	0
T15	194173	0	0	0
T16	103129	0	0	0
T28	0	1	0	0
T33	2472	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	4543	0	0	0
T80	62462	0	0	0
T147	1705	0	0	0
T148	1187	0	0	0
T149	58273	0	0	0
T150	1336	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	73042	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129870500	142	0	0
CgEnOn_A	129870500	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870500	142	0	0
T15	97085	0	0	0
T16	515647	0	0	0
T28	0	1	0	0
T33	1236	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	2271	0	0	0
T80	31231	0	0	0
T147	852	0	0	0
T148	592	0	0	0
T149	29136	0	0	0
T150	668	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	36521	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870500	142	0	0
T15	97085	0	0	0
T16	515647	0	0	0
T28	0	1	0	0
T33	1236	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	2271	0	0	0
T80	31231	0	0	0
T147	852	0	0	0
T148	592	0	0	0
T149	29136	0	0	0
T150	668	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	36521	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129870500	142	0	0
CgEnOn_A	129870500	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870500	142	0	0
T15	97085	0	0	0
T16	515647	0	0	0
T28	0	1	0	0
T33	1236	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	2271	0	0	0
T80	31231	0	0	0
T147	852	0	0	0
T148	592	0	0	0
T149	29136	0	0	0
T150	668	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	36521	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870500	142	0	0
T15	97085	0	0	0
T16	515647	0	0	0
T28	0	1	0	0
T33	1236	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	2271	0	0	0
T80	31231	0	0	0
T147	852	0	0	0
T148	592	0	0	0
T149	29136	0	0	0
T150	668	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	36521	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129870500	142	0	0
CgEnOn_A	129870500	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870500	142	0	0
T15	97085	0	0	0
T16	515647	0	0	0
T28	0	1	0	0
T33	1236	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	2271	0	0	0
T80	31231	0	0	0
T147	852	0	0	0
T148	592	0	0	0
T149	29136	0	0	0
T150	668	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	36521	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870500	142	0	0
T15	97085	0	0	0
T16	515647	0	0	0
T28	0	1	0	0
T33	1236	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	2271	0	0	0
T80	31231	0	0	0
T147	852	0	0	0
T148	592	0	0	0
T149	29136	0	0	0
T150	668	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	36521	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	520979236	142	0	0
CgEnOn_A	520979236	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520979236	142	0	0
T15	388774	0	0	0
T16	206261	0	0	0
T28	0	1	0	0
T33	5023	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	8551	0	0	0
T80	124949	0	0	0
T147	3543	0	0	0
T148	2171	0	0	0
T149	116611	0	0	0
T150	2600	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T174	146122	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520979236	135	0	0
T15	388774	0	0	0
T16	206261	0	0	0
T33	5023	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T56	0	1	0	0
T79	8551	0	0	0
T80	124949	0	0	0
T147	3543	0	0	0
T148	2171	0	0	0
T149	116611	0	0	0
T150	2600	0	0	0
T165	0	3	0	0
T166	0	6	0	0
T167	0	1	0	0
T168	0	6	0	0
T169	0	1	0	0
T171	0	4	0	0
T174	146122	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	553902368	153	0	0
CgEnOn_A	553902368	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	153	0	0
T11	105614	1	0	0
T12	963903	0	0	0
T27	175560	0	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T44	98511	0	0	0
T60	0	1	0	0
T63	5085	0	0	0
T165	0	4	0	0
T166	0	5	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T175	3933	0	0	0
T178	3982	0	0	0
T179	7477	0	0	0
T180	7799	0	0	0
T181	12082	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	147	0	0
T11	105614	1	0	0
T12	963903	0	0	0
T27	175560	0	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T44	98511	0	0	0
T63	5085	0	0	0
T165	0	4	0	0
T166	0	5	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	5	0	0
T175	3933	0	0	0
T178	3982	0	0	0
T179	7477	0	0	0
T180	7799	0	0	0
T181	12082	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	553902368	153	0	0
CgEnOn_A	553902368	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	153	0	0
T11	105614	1	0	0
T12	963903	0	0	0
T27	175560	0	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T44	98511	0	0	0
T60	0	1	0	0
T63	5085	0	0	0
T165	0	4	0	0
T166	0	5	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T175	3933	0	0	0
T178	3982	0	0	0
T179	7477	0	0	0
T180	7799	0	0	0
T181	12082	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	147	0	0
T11	105614	1	0	0
T12	963903	0	0	0
T27	175560	0	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T44	98511	0	0	0
T63	5085	0	0	0
T165	0	4	0	0
T166	0	5	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	5	0	0
T175	3933	0	0	0
T178	3982	0	0	0
T179	7477	0	0	0
T180	7799	0	0	0
T181	12082	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	265938401	145	0	0
CgEnOn_A	265938401	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265938401	145	0	0
T10	324430	1	0	0
T11	504335	0	0	0
T30	44095	0	0	0
T31	779	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	0	2	0	0
T38	1127	0	0	0
T39	1670	0	0	0
T40	4017	0	0	0
T41	1702	0	0	0
T42	2393	0	0	0
T43	1769	0	0	0
T165	0	3	0	0
T166	0	5	0	0
T168	0	6	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265938401	143	0	0
T15	205917	0	0	0
T16	104604	0	0	0
T33	2426	3	0	0
T34	0	4	0	0
T35	0	2	0	0
T79	4276	0	0	0
T80	71117	0	0	0
T147	1772	0	0	0
T148	1086	0	0	0
T149	61188	0	0	0
T150	1300	0	0	0
T165	0	3	0	0
T166	0	5	0	0
T168	0	6	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	87464	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129870500	8182	0	0
CgEnOn_A	129870500	5794	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870500	8182	0	0
T1	202735	41	0	0
T2	45697	1	0	0
T4	19440	19	0	0
T5	2021	1	0	0
T6	2263	1	0	0
T7	563	1	0	0
T17	1117	1	0	0
T24	986	1	0	0
T25	370	1	0	0
T26	704	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870500	5794	0	0
T1	202735	28	0	0
T2	45697	0	0	0
T3	0	15	0	0
T4	19440	0	0	0
T10	0	73	0	0
T11	0	144	0	0
T12	0	23	0	0
T17	1117	0	0	0
T18	1497	0	0	0
T19	519	0	0	0
T20	1450	0	0	0
T21	3970	0	0	0
T22	4006	0	0	0
T23	966	0	0	0
T27	0	30	0	0
T97	0	3	0	0
T175	0	13	0	0
T176	0	8	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	259742289	8229	0	0
CgEnOn_A	259742289	5841	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259742289	8229	0	0
T1	405481	45	0	0
T2	91394	1	0	0
T4	38883	19	0	0
T5	4047	1	0	0
T6	4525	1	0	0
T7	1126	1	0	0
T17	2235	1	0	0
T24	1975	1	0	0
T25	739	1	0	0
T26	1409	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259742289	5841	0	0
T1	405481	32	0	0
T2	91394	0	0	0
T3	0	18	0	0
T4	38883	0	0	0
T10	0	75	0	0
T11	0	150	0	0
T12	0	24	0	0
T17	2235	0	0	0
T18	2995	0	0	0
T19	1039	0	0	0
T20	2901	0	0	0
T21	7941	0	0	0
T22	8013	0	0	0
T23	1934	0	0	0
T27	0	32	0	0
T97	0	3	0	0
T175	0	13	0	0
T176	0	8	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	520979236	8222	0	0
CgEnOn_A	520979236	5827	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520979236	8222	0	0
T1	810747	41	0	0
T2	182841	1	0	0
T4	134474	19	0	0
T5	6932	1	0	0
T6	9089	1	0	0
T7	2372	2	0	0
T17	4168	1	0	0
T24	3712	1	0	0
T25	1557	1	0	0
T26	1571	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520979236	5827	0	0
T1	810747	28	0	0
T2	182841	0	0	0
T3	0	20	0	0
T4	134474	0	0	0
T7	2372	1	0	0
T10	0	77	0	0
T11	0	146	0	0
T12	0	24	0	0
T17	4168	0	0	0
T18	6056	0	0	0
T19	2083	0	0	0
T24	3712	0	0	0
T25	1557	0	0	0
T26	1571	0	0	0
T27	0	34	0	0
T97	0	2	0	0
T175	0	14	0	0
T176	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	265938401	8220	0	0
CgEnOn_A	265938401	5823	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265938401	8220	0	0
T1	465873	43	0	0
T2	91424	1	0	0
T4	67240	19	0	0
T5	3466	1	0	0
T6	4544	1	0	0
T7	1186	2	0	0
T17	2084	1	0	0
T24	1856	1	0	0
T25	779	1	0	0
T26	785	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265938401	5823	0	0
T1	465873	30	0	0
T2	91424	0	0	0
T3	0	22	0	0
T4	67240	0	0	0
T7	1186	1	0	0
T10	0	74	0	0
T11	0	146	0	0
T12	0	23	0	0
T17	2084	0	0	0
T18	3028	0	0	0
T19	1041	0	0	0
T24	1856	0	0	0
T25	779	0	0	0
T26	785	0	0	0
T27	0	30	0	0
T97	0	2	0	0
T175	0	13	0	0
T176	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Covered	T6,T7,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	553902368	4132	0	0
CgEnOn_A	553902368	4126	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	4132	0	0
T1	964553	4	0	0
T2	190465	0	0	0
T3	0	11	0	0
T4	140082	0	0	0
T6	9468	8	0	0
T7	2471	1	0	0
T10	0	43	0	0
T11	0	105	0	0
T17	4341	0	0	0
T18	6308	8	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1636	0	0	0
T41	0	14	0	0
T110	0	1	0	0
T111	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	4126	0	0
T1	964553	4	0	0
T2	190465	0	0	0
T3	0	11	0	0
T4	140082	0	0	0
T6	9468	8	0	0
T7	2471	1	0	0
T10	0	43	0	0
T11	0	105	0	0
T17	4341	0	0	0
T18	6308	8	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1636	0	0	0
T41	0	14	0	0
T110	0	1	0	0
T111	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Covered	T6,T7,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	553902368	4170	0	0
CgEnOn_A	553902368	4164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	4170	0	0
T1	964553	4	0	0
T2	190465	0	0	0
T3	0	15	0	0
T4	140082	0	0	0
T6	9468	10	0	0
T7	2471	1	0	0
T10	0	45	0	0
T11	0	108	0	0
T17	4341	0	0	0
T18	6308	8	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1636	0	0	0
T41	0	10	0	0
T110	0	1	0	0
T111	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	4164	0	0
T1	964553	4	0	0
T2	190465	0	0	0
T3	0	15	0	0
T4	140082	0	0	0
T6	9468	10	0	0
T7	2471	1	0	0
T10	0	45	0	0
T11	0	108	0	0
T17	4341	0	0	0
T18	6308	8	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1636	0	0	0
T41	0	10	0	0
T110	0	1	0	0
T111	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Covered	T6,T7,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	553902368	4201	0	0
CgEnOn_A	553902368	4195	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	4201	0	0
T1	964553	4	0	0
T2	190465	0	0	0
T3	0	13	0	0
T4	140082	0	0	0
T6	9468	9	0	0
T7	2471	1	0	0
T10	0	44	0	0
T11	0	105	0	0
T17	4341	0	0	0
T18	6308	7	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1636	0	0	0
T41	0	7	0	0
T110	0	1	0	0
T111	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	4195	0	0
T1	964553	4	0	0
T2	190465	0	0	0
T3	0	13	0	0
T4	140082	0	0	0
T6	9468	9	0	0
T7	2471	1	0	0
T10	0	44	0	0
T11	0	105	0	0
T17	4341	0	0	0
T18	6308	7	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1636	0	0	0
T41	0	7	0	0
T110	0	1	0	0
T111	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Covered	T6,T7,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	553902368	4115	0	0
CgEnOn_A	553902368	4109	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	4115	0	0
T1	964553	4	0	0
T2	190465	0	0	0
T3	0	11	0	0
T4	140082	0	0	0
T6	9468	8	0	0
T7	2471	1	0	0
T10	0	54	0	0
T11	0	94	0	0
T17	4341	0	0	0
T18	6308	6	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1636	0	0	0
T41	0	8	0	0
T110	0	1	0	0
T111	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553902368	4109	0	0
T1	964553	4	0	0
T2	190465	0	0	0
T3	0	11	0	0
T4	140082	0	0	0
T6	9468	8	0	0
T7	2471	1	0	0
T10	0	54	0	0
T11	0	94	0	0
T17	4341	0	0	0
T18	6308	6	0	0
T24	3867	0	0	0
T25	1622	0	0	0
T26	1636	0	0	0
T41	0	8	0	0
T110	0	1	0	0
T111	0	6	0	0