Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	593763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3329974

1

T1

121521

T6

20

T7

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	963715	1			T1	33381		T6	17		T7	13
values[0x0]	1360669	1			T1	48882		T6	22		T7	12
values[0x1]	1599353	1			T1	57858		T6	13		T7	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	329735	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3594002

1

T1

130478

T6

25

T7

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15014	1			T1	558		T5	2		T2	405
valid_sources[0x01]	15837	1			T1	639		T2	182		T3	338
valid_sources[0x02]	14701	1			T1	647		T5	1		T2	151
valid_sources[0x03]	16647	1			T1	466		T5	1		T2	578
valid_sources[0x04]	15959	1			T1	583		T6	1		T5	1
valid_sources[0x05]	14973	1			T1	420		T2	306		T3	497
valid_sources[0x06]	16675	1			T1	538		T2	730		T3	636
valid_sources[0x07]	15370	1			T1	524		T19	2		T3	593
valid_sources[0x08]	14460	1			T1	527		T2	15		T3	402
valid_sources[0x09]	15353	1			T1	623		T5	3		T2	507
valid_sources[0x0a]	14649	1			T1	506		T5	1		T2	1
valid_sources[0x0b]	15789	1			T1	625		T6	1		T7	8
valid_sources[0x0c]	14705	1			T1	405		T5	2		T2	7
valid_sources[0x0d]	16145	1			T1	467		T5	1		T2	420
valid_sources[0x0e]	15402	1			T1	473		T5	2		T2	48
valid_sources[0x0f]	15099	1			T1	542		T2	980		T3	619
valid_sources[0x10]	14414	1			T1	521		T6	1		T2	9
valid_sources[0x11]	15005	1			T1	558		T5	1		T2	345
valid_sources[0x12]	17091	1			T1	444		T5	4		T2	938
valid_sources[0x13]	14562	1			T1	389		T5	2		T2	74
valid_sources[0x14]	14615	1			T1	548		T2	249		T3	325
valid_sources[0x15]	14585	1			T1	595		T5	1		T2	66
valid_sources[0x16]	16102	1			T1	554		T5	1		T2	143
valid_sources[0x17]	14614	1			T1	537		T6	1		T2	16
valid_sources[0x18]	14381	1			T1	622		T6	1		T5	1
valid_sources[0x19]	14802	1			T1	486		T5	1		T2	323
valid_sources[0x1a]	15736	1			T1	493		T5	1		T2	20
valid_sources[0x1b]	14931	1			T1	679		T6	1		T2	185
valid_sources[0x1c]	15963	1			T1	579		T2	362		T3	330
valid_sources[0x1d]	14182	1			T1	596		T5	1		T2	112
valid_sources[0x1e]	15391	1			T1	476		T5	2		T19	1
valid_sources[0x1f]	16531	1			T1	618		T6	1		T18	9
valid_sources[0x20]	15038	1			T1	588		T5	1		T2	18
valid_sources[0x21]	15604	1			T1	493		T2	1		T3	346
valid_sources[0x22]	15195	1			T1	597		T5	2		T2	509
valid_sources[0x23]	14698	1			T1	438		T5	1		T19	2
valid_sources[0x24]	13380	1			T1	517		T5	4		T2	589
valid_sources[0x25]	15952	1			T1	525		T5	1		T2	380
valid_sources[0x26]	14285	1			T1	424		T2	168		T3	482
valid_sources[0x27]	15972	1			T1	600		T5	1		T2	250
valid_sources[0x28]	14948	1			T1	605		T7	2		T5	1
valid_sources[0x29]	15480	1			T1	692		T5	1		T19	3
valid_sources[0x2a]	15240	1			T1	482		T4	564		T2	410
valid_sources[0x2b]	16349	1			T1	669		T5	1		T2	426
valid_sources[0x2c]	16192	1			T1	476		T2	361		T3	571
valid_sources[0x2d]	15436	1			T1	502		T5	3		T2	42
valid_sources[0x2e]	15327	1			T1	503		T2	226		T3	471
valid_sources[0x2f]	14973	1			T1	534		T5	1		T3	355
valid_sources[0x30]	17378	1			T1	632		T5	3		T2	90
valid_sources[0x31]	15577	1			T1	557		T5	1		T2	491
valid_sources[0x32]	16093	1			T1	561		T6	1		T5	2
valid_sources[0x33]	15026	1			T1	606		T5	1		T2	481
valid_sources[0x34]	15523	1			T1	476		T5	3		T2	574
valid_sources[0x35]	17225	1			T1	608		T19	2		T2	350
valid_sources[0x36]	15821	1			T1	560		T5	1		T2	216
valid_sources[0x37]	14386	1			T1	482		T5	2		T2	219
valid_sources[0x38]	15877	1			T1	523		T5	1		T2	25
valid_sources[0x39]	15069	1			T1	537		T5	2		T3	471
valid_sources[0x3a]	15216	1			T1	414		T7	2		T5	1
valid_sources[0x3b]	16860	1			T1	499		T5	1		T2	118
valid_sources[0x3c]	13720	1			T1	587		T6	1		T5	2
valid_sources[0x3d]	14868	1			T1	366		T5	4		T2	274
valid_sources[0x3e]	15031	1			T1	605		T2	132		T3	418
valid_sources[0x3f]	15755	1			T1	649		T5	1		T2	11
valid_sources[0x40]	14792	1			T1	541		T2	155		T3	445
valid_sources[0x41]	14942	1			T1	470		T2	17		T3	338
valid_sources[0x42]	17693	1			T1	633		T5	1		T2	530
valid_sources[0x43]	15364	1			T1	511		T5	4		T2	769
valid_sources[0x44]	15985	1			T1	561		T5	2		T2	955
valid_sources[0x45]	15395	1			T1	517		T5	4		T2	17
valid_sources[0x46]	15224	1			T1	536		T6	1		T2	288
valid_sources[0x47]	15545	1			T1	667		T7	1		T5	1
valid_sources[0x48]	16313	1			T1	573		T6	1		T5	2
valid_sources[0x49]	16424	1			T1	507		T7	4		T5	1
valid_sources[0x4a]	14660	1			T1	426		T2	177		T3	341
valid_sources[0x4b]	15756	1			T1	685		T5	7		T2	397
valid_sources[0x4c]	14922	1			T1	434		T6	2		T2	298
valid_sources[0x4d]	14769	1			T1	758		T5	1		T2	121
valid_sources[0x4e]	14909	1			T1	586		T6	1		T5	4
valid_sources[0x4f]	14189	1			T1	531		T5	1		T3	548
valid_sources[0x50]	13584	1			T1	547		T6	1		T2	186
valid_sources[0x51]	15072	1			T1	527		T5	2		T2	152
valid_sources[0x52]	16154	1			T1	569		T7	2		T5	1
valid_sources[0x53]	14811	1			T1	529		T5	1		T2	315
valid_sources[0x54]	14246	1			T1	590		T5	2		T2	189
valid_sources[0x55]	14063	1			T1	637		T5	4		T2	49
valid_sources[0x56]	15171	1			T1	615		T6	1		T5	2
valid_sources[0x57]	15109	1			T1	623		T5	1		T2	77
valid_sources[0x58]	14390	1			T1	688		T5	3		T2	11
valid_sources[0x59]	16144	1			T1	533		T5	2		T2	9
valid_sources[0x5a]	15312	1			T1	461		T5	1		T2	434
valid_sources[0x5b]	14474	1			T1	530		T2	70		T3	410
valid_sources[0x5c]	14426	1			T1	503		T5	1		T2	119
valid_sources[0x5d]	15820	1			T1	456		T5	3		T2	149
valid_sources[0x5e]	14998	1			T1	523		T5	1		T3	502
valid_sources[0x5f]	15677	1			T1	609		T6	1		T2	8
valid_sources[0x60]	15385	1			T1	699		T6	1		T19	1
valid_sources[0x61]	15476	1			T1	569		T5	2		T2	53
valid_sources[0x62]	15555	1			T1	537		T6	2		T2	334
valid_sources[0x63]	15121	1			T1	639		T5	5		T2	7
valid_sources[0x64]	16117	1			T1	449		T2	64		T3	470
valid_sources[0x65]	16262	1			T1	410		T6	1		T5	3
valid_sources[0x66]	16606	1			T1	459		T7	4		T2	332
valid_sources[0x67]	16045	1			T1	454		T5	1		T2	406
valid_sources[0x68]	14355	1			T1	448		T3	453		T10	257
valid_sources[0x69]	14962	1			T1	421		T5	2		T2	262
valid_sources[0x6a]	16013	1			T1	592		T5	2		T2	2
valid_sources[0x6b]	15366	1			T1	524		T5	3		T2	156
valid_sources[0x6c]	15598	1			T1	635		T5	3		T3	596
valid_sources[0x6d]	14285	1			T1	635		T2	2		T3	320
valid_sources[0x6e]	14573	1			T1	604		T2	96		T3	472
valid_sources[0x6f]	16179	1			T1	666		T2	219		T3	486
valid_sources[0x70]	14729	1			T1	452		T5	3		T19	2
valid_sources[0x71]	15276	1			T1	589		T2	435		T3	483
valid_sources[0x72]	15529	1			T1	468		T5	5		T2	207
valid_sources[0x73]	14602	1			T1	559		T5	1		T2	21
valid_sources[0x74]	15702	1			T1	438		T5	1		T2	270
valid_sources[0x75]	15202	1			T1	746		T6	1		T2	380
valid_sources[0x76]	14334	1			T1	692		T5	1		T2	259
valid_sources[0x77]	14683	1			T1	532		T5	1		T3	399
valid_sources[0x78]	16437	1			T1	585		T5	1		T2	139
valid_sources[0x79]	15586	1			T1	514		T5	1		T2	1381
valid_sources[0x7a]	15418	1			T1	526		T2	127		T3	412
valid_sources[0x7b]	16435	1			T1	482		T6	1		T5	1
valid_sources[0x7c]	15645	1			T1	588		T6	1		T5	3
valid_sources[0x7d]	14884	1			T1	483		T2	276		T3	477
valid_sources[0x7e]	16027	1			T1	493		T2	148		T3	436
valid_sources[0x7f]	15260	1			T1	508		T6	1		T5	1
valid_sources[0x80]	16729	1			T1	537		T5	3		T3	456

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

840678

1

T1

30216

T6

10

T7

8

values[0x0]

all_enables

biggest_size

1267827

1

T1

46318

T6

8

T7

4

values[0x1]

all_enables

biggest_size

1221469

1

T1

44987

T6

2

T7

3