Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T17,T30,T31
1	1	Covered	T1,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1032208412	14454	0	0
GateOpen_A	1032208412	20939	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032208412	14454	0	0
T1	987623	328	0	0
T2	976670	221	0	0
T3	0	403	0	0
T4	144237	0	0	0
T5	341871	0	0	0
T6	20133	0	0	0
T7	5337	0	0	0
T10	0	177	0	0
T11	0	175	0	0
T17	3425	15	0	0
T18	2819	0	0	0
T19	3292	0	0	0
T20	14047	0	0	0
T22	0	20	0	0
T58	0	4	0	0
T63	0	4	0	0
T131	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032208412	20939	0	0
T1	987623	356	0	0
T2	976670	235	0	0
T3	0	431	0	0
T4	144237	52	0	0
T5	341871	4	0	0
T6	20133	0	0	0
T7	5337	4	0	0
T17	3425	19	0	0
T18	2819	0	0	0
T19	3292	4	0	0
T20	14047	4	0	0
T21	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T17,T30,T31
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	113837299	3470	0	0
GateOpen_A	113837299	5090	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113837299	3470	0	0
T1	548158	82	0	0
T2	107236	57	0	0
T3	0	103	0	0
T4	10495	0	0	0
T5	36699	0	0	0
T6	2461	0	0	0
T7	630	0	0	0
T10	0	36	0	0
T11	0	39	0	0
T17	360	4	0	0
T18	309	0	0	0
T19	346	0	0	0
T20	1555	0	0	0
T22	0	5	0	0
T58	0	1	0	0
T63	0	1	0	0
T131	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113837299	5090	0	0
T1	548158	89	0	0
T2	107236	60	0	0
T3	0	110	0	0
T4	10495	13	0	0
T5	36699	1	0	0
T6	2461	0	0	0
T7	630	1	0	0
T17	360	5	0	0
T18	309	0	0	0
T19	346	1	0	0
T20	1555	1	0	0
T21	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T17,T30,T31
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	227675429	3669	0	0
GateOpen_A	227675429	5289	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675429	3669	0	0
T1	109631	79	0	0
T2	214473	55	0	0
T3	0	103	0	0
T4	20987	0	0	0
T5	73398	0	0	0
T6	4924	0	0	0
T7	1261	0	0	0
T10	0	50	0	0
T11	0	45	0	0
T17	719	4	0	0
T18	618	0	0	0
T19	691	0	0	0
T20	3109	0	0	0
T22	0	6	0	0
T58	0	1	0	0
T63	0	1	0	0
T131	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675429	5289	0	0
T1	109631	86	0	0
T2	214473	58	0	0
T3	0	110	0	0
T4	20987	13	0	0
T5	73398	1	0	0
T6	4924	0	0	0
T7	1261	1	0	0
T17	719	5	0	0
T18	618	0	0	0
T19	691	1	0	0
T20	3109	1	0	0
T21	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T17,T30,T31
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	456926531	3647	0	0
GateOpen_A	456926531	5269	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926531	3647	0	0
T1	219137	82	0	0
T2	429532	55	0	0
T3	0	96	0	0
T4	75169	0	0	0
T5	146834	0	0	0
T6	8498	0	0	0
T7	2297	0	0	0
T10	0	42	0	0
T11	0	45	0	0
T17	1557	4	0	0
T18	1261	0	0	0
T19	1503	0	0	0
T20	6255	0	0	0
T22	0	5	0	0
T58	0	1	0	0
T63	0	1	0	0
T131	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926531	5269	0	0
T1	219137	89	0	0
T2	429532	59	0	0
T3	0	103	0	0
T4	75169	13	0	0
T5	146834	1	0	0
T6	8498	0	0	0
T7	2297	1	0	0
T17	1557	5	0	0
T18	1261	0	0	0
T19	1503	1	0	0
T20	6255	1	0	0
T21	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T17,T30,T31
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	233769153	3668	0	0
GateOpen_A	233769153	5291	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233769153	3668	0	0
T1	110697	85	0	0
T2	225429	54	0	0
T3	0	101	0	0
T4	37586	0	0	0
T5	84940	0	0	0
T6	4250	0	0	0
T7	1149	0	0	0
T10	0	49	0	0
T11	0	46	0	0
T17	789	3	0	0
T18	631	0	0	0
T19	752	0	0	0
T20	3128	0	0	0
T22	0	4	0	0
T58	0	1	0	0
T63	0	1	0	0
T131	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233769153	5291	0	0
T1	110697	92	0	0
T2	225429	58	0	0
T3	0	108	0	0
T4	37586	13	0	0
T5	84940	1	0	0
T6	4250	0	0	0
T7	1149	1	0	0
T17	789	4	0	0
T18	631	0	0	0
T19	752	1	0	0
T20	3128	1	0	0
T21	0	4	0	0