Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	752465540	68827	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752465540	68827	0	0
T1	2673480	1074	0	0
T2	1196590	458	0	0
T3	0	1000	0	0
T4	387605	0	0	0
T5	467900	0	0	0
T6	10620	0	0	0
T7	11725	0	0	0
T10	0	317	0	0
T11	0	1629	0	0
T12	0	333	0	0
T13	0	77	0	0
T14	0	87	0	0
T15	0	205	0	0
T16	0	222	0	0
T17	8575	0	0	0
T18	6565	0	0	0
T19	7745	0	0	0
T20	4235	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150493108	10404	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	10404	0	0
T1	534696	171	0	0
T2	239318	68	0	0
T3	0	160	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	0	0	0
T7	2345	0	0	0
T10	0	46	0	0
T11	0	216	0	0
T12	0	49	0	0
T13	0	11	0	0
T14	0	15	0	0
T15	0	29	0	0
T16	0	36	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150493108	10157	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	10157	0	0
T1	534696	166	0	0
T2	239318	66	0	0
T3	0	160	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	0	0	0
T7	2345	0	0	0
T10	0	46	0	0
T11	0	213	0	0
T12	0	49	0	0
T13	0	11	0	0
T14	0	13	0	0
T15	0	29	0	0
T16	0	36	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150493108	13802	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	13802	0	0
T1	534696	219	0	0
T2	239318	91	0	0
T3	0	202	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	0	0	0
T7	2345	0	0	0
T10	0	64	0	0
T11	0	332	0	0
T12	0	66	0	0
T13	0	15	0	0
T14	0	17	0	0
T15	0	42	0	0
T16	0	45	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150493108	13859	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	13859	0	0
T1	534696	217	0	0
T2	239318	92	0	0
T3	0	202	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	0	0	0
T7	2345	0	0	0
T10	0	63	0	0
T11	0	329	0	0
T12	0	66	0	0
T13	0	16	0	0
T14	0	19	0	0
T15	0	41	0	0
T16	0	46	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	150493108	20605	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	20605	0	0
T1	534696	301	0	0
T2	239318	141	0	0
T3	0	276	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	0	0	0
T7	2345	0	0	0
T10	0	98	0	0
T11	0	539	0	0
T12	0	103	0	0
T13	0	24	0	0
T14	0	23	0	0
T15	0	64	0	0
T16	0	59	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0