Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
10772899 |
10764129 |
0 |
0 |
T2 |
8988778 |
8954304 |
0 |
0 |
T4 |
2009425 |
276844 |
0 |
0 |
T5 |
3445426 |
3443126 |
0 |
0 |
T6 |
138042 |
136031 |
0 |
0 |
T7 |
61989 |
55862 |
0 |
0 |
T17 |
43506 |
37688 |
0 |
0 |
T18 |
34276 |
32307 |
0 |
0 |
T19 |
40562 |
34771 |
0 |
0 |
T20 |
90792 |
89494 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
902958648 |
888679956 |
0 |
14490 |
T1 |
3208176 |
3205284 |
0 |
18 |
T2 |
1435908 |
1429440 |
0 |
18 |
T4 |
465126 |
35868 |
0 |
18 |
T5 |
561480 |
561060 |
0 |
18 |
T6 |
12744 |
12522 |
0 |
18 |
T7 |
14070 |
12552 |
0 |
18 |
T17 |
10290 |
8832 |
0 |
18 |
T18 |
7878 |
7362 |
0 |
18 |
T19 |
9294 |
7848 |
0 |
18 |
T20 |
5082 |
4980 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
2213149 |
2211149 |
0 |
21 |
T2 |
2789112 |
2777606 |
0 |
21 |
T4 |
543423 |
41902 |
0 |
21 |
T5 |
1065817 |
1064963 |
0 |
21 |
T6 |
48158 |
47370 |
0 |
21 |
T7 |
16555 |
14769 |
0 |
21 |
T17 |
11439 |
9747 |
0 |
21 |
T18 |
9138 |
8539 |
0 |
21 |
T19 |
10860 |
9172 |
0 |
21 |
T20 |
34009 |
33404 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
195205 |
0 |
0 |
T1 |
2213149 |
5190 |
0 |
0 |
T2 |
2789112 |
1908 |
0 |
0 |
T3 |
0 |
846 |
0 |
0 |
T4 |
543423 |
52 |
0 |
0 |
T5 |
1065817 |
4 |
0 |
0 |
T6 |
48158 |
223 |
0 |
0 |
T7 |
16555 |
211 |
0 |
0 |
T10 |
0 |
805 |
0 |
0 |
T11 |
0 |
587 |
0 |
0 |
T13 |
0 |
90 |
0 |
0 |
T17 |
11439 |
36 |
0 |
0 |
T18 |
9138 |
12 |
0 |
0 |
T19 |
10860 |
12 |
0 |
0 |
T20 |
34009 |
12 |
0 |
0 |
T61 |
0 |
145 |
0 |
0 |
T62 |
0 |
9 |
0 |
0 |
T108 |
0 |
76 |
0 |
0 |
T109 |
0 |
7 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5351574 |
5347660 |
0 |
0 |
T2 |
4763758 |
4747240 |
0 |
0 |
T4 |
1000876 |
198567 |
0 |
0 |
T5 |
1818129 |
1817064 |
0 |
0 |
T6 |
77140 |
76100 |
0 |
0 |
T7 |
31364 |
28502 |
0 |
0 |
T17 |
21777 |
19070 |
0 |
0 |
T18 |
17260 |
16367 |
0 |
0 |
T19 |
20408 |
17712 |
0 |
0 |
T20 |
51701 |
51071 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456926071 |
452678296 |
0 |
0 |
T1 |
219137 |
218937 |
0 |
0 |
T2 |
429532 |
428032 |
0 |
0 |
T4 |
75169 |
5833 |
0 |
0 |
T5 |
146833 |
146698 |
0 |
0 |
T6 |
8498 |
8363 |
0 |
0 |
T7 |
2297 |
2052 |
0 |
0 |
T17 |
1557 |
1326 |
0 |
0 |
T18 |
1260 |
1180 |
0 |
0 |
T19 |
1502 |
1271 |
0 |
0 |
T20 |
6255 |
6147 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456926071 |
452671387 |
0 |
2415 |
T1 |
219137 |
218937 |
0 |
3 |
T2 |
429532 |
428030 |
0 |
3 |
T4 |
75169 |
5794 |
0 |
3 |
T5 |
146833 |
146695 |
0 |
3 |
T6 |
8498 |
8360 |
0 |
3 |
T7 |
2297 |
2049 |
0 |
3 |
T17 |
1557 |
1323 |
0 |
3 |
T18 |
1260 |
1177 |
0 |
3 |
T19 |
1502 |
1268 |
0 |
3 |
T20 |
6255 |
6144 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456926071 |
27459 |
0 |
0 |
T1 |
219137 |
708 |
0 |
0 |
T2 |
429532 |
211 |
0 |
0 |
T3 |
0 |
357 |
0 |
0 |
T4 |
75169 |
0 |
0 |
0 |
T5 |
146833 |
0 |
0 |
0 |
T6 |
8498 |
84 |
0 |
0 |
T7 |
2297 |
79 |
0 |
0 |
T10 |
0 |
333 |
0 |
0 |
T11 |
0 |
242 |
0 |
0 |
T17 |
1557 |
0 |
0 |
0 |
T18 |
1260 |
0 |
0 |
0 |
T19 |
1502 |
0 |
0 |
0 |
T20 |
6255 |
0 |
0 |
0 |
T61 |
0 |
84 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
T109 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148113326 |
0 |
2415 |
T1 |
534696 |
534214 |
0 |
3 |
T2 |
239318 |
238240 |
0 |
3 |
T4 |
77521 |
5978 |
0 |
3 |
T5 |
93580 |
93510 |
0 |
3 |
T6 |
2124 |
2087 |
0 |
3 |
T7 |
2345 |
2092 |
0 |
3 |
T17 |
1715 |
1472 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1549 |
1308 |
0 |
3 |
T20 |
847 |
830 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
16904 |
0 |
0 |
T1 |
534696 |
491 |
0 |
0 |
T2 |
239318 |
141 |
0 |
0 |
T3 |
0 |
224 |
0 |
0 |
T4 |
77521 |
0 |
0 |
0 |
T5 |
93580 |
0 |
0 |
0 |
T6 |
2124 |
32 |
0 |
0 |
T7 |
2345 |
31 |
0 |
0 |
T10 |
0 |
220 |
0 |
0 |
T11 |
0 |
164 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T61 |
0 |
30 |
0 |
0 |
T62 |
0 |
4 |
0 |
0 |
T109 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148113326 |
0 |
2415 |
T1 |
534696 |
534214 |
0 |
3 |
T2 |
239318 |
238240 |
0 |
3 |
T4 |
77521 |
5978 |
0 |
3 |
T5 |
93580 |
93510 |
0 |
3 |
T6 |
2124 |
2087 |
0 |
3 |
T7 |
2345 |
2092 |
0 |
3 |
T17 |
1715 |
1472 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1549 |
1308 |
0 |
3 |
T20 |
847 |
830 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
19474 |
0 |
0 |
T1 |
534696 |
522 |
0 |
0 |
T2 |
239318 |
172 |
0 |
0 |
T3 |
0 |
265 |
0 |
0 |
T4 |
77521 |
0 |
0 |
0 |
T5 |
93580 |
0 |
0 |
0 |
T6 |
2124 |
41 |
0 |
0 |
T7 |
2345 |
36 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T11 |
0 |
181 |
0 |
0 |
T13 |
0 |
90 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T61 |
0 |
31 |
0 |
0 |
T108 |
0 |
76 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
484768610 |
0 |
0 |
T1 |
231155 |
231067 |
0 |
0 |
T2 |
470236 |
469347 |
0 |
0 |
T4 |
78303 |
43720 |
0 |
0 |
T5 |
182956 |
182915 |
0 |
0 |
T6 |
8853 |
8741 |
0 |
0 |
T7 |
2392 |
2252 |
0 |
0 |
T17 |
1613 |
1487 |
0 |
0 |
T18 |
1313 |
1287 |
0 |
0 |
T19 |
1565 |
1439 |
0 |
0 |
T20 |
6515 |
6475 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
484768610 |
0 |
0 |
T1 |
231155 |
231067 |
0 |
0 |
T2 |
470236 |
469347 |
0 |
0 |
T4 |
78303 |
43720 |
0 |
0 |
T5 |
182956 |
182915 |
0 |
0 |
T6 |
8853 |
8741 |
0 |
0 |
T7 |
2392 |
2252 |
0 |
0 |
T17 |
1613 |
1487 |
0 |
0 |
T18 |
1313 |
1287 |
0 |
0 |
T19 |
1565 |
1439 |
0 |
0 |
T20 |
6515 |
6475 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456926071 |
454779361 |
0 |
0 |
T1 |
219137 |
219053 |
0 |
0 |
T2 |
429532 |
428724 |
0 |
0 |
T4 |
75169 |
41970 |
0 |
0 |
T5 |
146833 |
146794 |
0 |
0 |
T6 |
8498 |
8391 |
0 |
0 |
T7 |
2297 |
2162 |
0 |
0 |
T17 |
1557 |
1436 |
0 |
0 |
T18 |
1260 |
1235 |
0 |
0 |
T19 |
1502 |
1381 |
0 |
0 |
T20 |
6255 |
6216 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456926071 |
454779361 |
0 |
0 |
T1 |
219137 |
219053 |
0 |
0 |
T2 |
429532 |
428724 |
0 |
0 |
T4 |
75169 |
41970 |
0 |
0 |
T5 |
146833 |
146794 |
0 |
0 |
T6 |
8498 |
8391 |
0 |
0 |
T7 |
2297 |
2162 |
0 |
0 |
T17 |
1557 |
1436 |
0 |
0 |
T18 |
1260 |
1235 |
0 |
0 |
T19 |
1502 |
1381 |
0 |
0 |
T20 |
6255 |
6216 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
227675037 |
227675037 |
0 |
0 |
T1 |
109631 |
109631 |
0 |
0 |
T2 |
214473 |
214473 |
0 |
0 |
T4 |
20987 |
20987 |
0 |
0 |
T5 |
73397 |
73397 |
0 |
0 |
T6 |
4924 |
4924 |
0 |
0 |
T7 |
1260 |
1260 |
0 |
0 |
T17 |
718 |
718 |
0 |
0 |
T18 |
618 |
618 |
0 |
0 |
T19 |
691 |
691 |
0 |
0 |
T20 |
3108 |
3108 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
227675037 |
227675037 |
0 |
0 |
T1 |
109631 |
109631 |
0 |
0 |
T2 |
214473 |
214473 |
0 |
0 |
T4 |
20987 |
20987 |
0 |
0 |
T5 |
73397 |
73397 |
0 |
0 |
T6 |
4924 |
4924 |
0 |
0 |
T7 |
1260 |
1260 |
0 |
0 |
T17 |
718 |
718 |
0 |
0 |
T18 |
618 |
618 |
0 |
0 |
T19 |
691 |
691 |
0 |
0 |
T20 |
3108 |
3108 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113836900 |
113836900 |
0 |
0 |
T1 |
548158 |
548158 |
0 |
0 |
T2 |
107236 |
107236 |
0 |
0 |
T4 |
10494 |
10494 |
0 |
0 |
T5 |
36699 |
36699 |
0 |
0 |
T6 |
2460 |
2460 |
0 |
0 |
T7 |
629 |
629 |
0 |
0 |
T17 |
359 |
359 |
0 |
0 |
T18 |
309 |
309 |
0 |
0 |
T19 |
345 |
345 |
0 |
0 |
T20 |
1554 |
1554 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113836900 |
113836900 |
0 |
0 |
T1 |
548158 |
548158 |
0 |
0 |
T2 |
107236 |
107236 |
0 |
0 |
T4 |
10494 |
10494 |
0 |
0 |
T5 |
36699 |
36699 |
0 |
0 |
T6 |
2460 |
2460 |
0 |
0 |
T7 |
629 |
629 |
0 |
0 |
T17 |
359 |
359 |
0 |
0 |
T18 |
309 |
309 |
0 |
0 |
T19 |
345 |
345 |
0 |
0 |
T20 |
1554 |
1554 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233768724 |
232680154 |
0 |
0 |
T1 |
110697 |
110655 |
0 |
0 |
T2 |
225429 |
224910 |
0 |
0 |
T4 |
37585 |
20986 |
0 |
0 |
T5 |
84940 |
84921 |
0 |
0 |
T6 |
4249 |
4196 |
0 |
0 |
T7 |
1148 |
1081 |
0 |
0 |
T17 |
788 |
728 |
0 |
0 |
T18 |
630 |
618 |
0 |
0 |
T19 |
751 |
690 |
0 |
0 |
T20 |
3127 |
3108 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233768724 |
232680154 |
0 |
0 |
T1 |
110697 |
110655 |
0 |
0 |
T2 |
225429 |
224910 |
0 |
0 |
T4 |
37585 |
20986 |
0 |
0 |
T5 |
84940 |
84921 |
0 |
0 |
T6 |
4249 |
4196 |
0 |
0 |
T7 |
1148 |
1081 |
0 |
0 |
T17 |
788 |
728 |
0 |
0 |
T18 |
630 |
618 |
0 |
0 |
T19 |
751 |
690 |
0 |
0 |
T20 |
3127 |
3108 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148113326 |
0 |
2415 |
T1 |
534696 |
534214 |
0 |
3 |
T2 |
239318 |
238240 |
0 |
3 |
T4 |
77521 |
5978 |
0 |
3 |
T5 |
93580 |
93510 |
0 |
3 |
T6 |
2124 |
2087 |
0 |
3 |
T7 |
2345 |
2092 |
0 |
3 |
T17 |
1715 |
1472 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1549 |
1308 |
0 |
3 |
T20 |
847 |
830 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148113326 |
0 |
2415 |
T1 |
534696 |
534214 |
0 |
3 |
T2 |
239318 |
238240 |
0 |
3 |
T4 |
77521 |
5978 |
0 |
3 |
T5 |
93580 |
93510 |
0 |
3 |
T6 |
2124 |
2087 |
0 |
3 |
T7 |
2345 |
2092 |
0 |
3 |
T17 |
1715 |
1472 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1549 |
1308 |
0 |
3 |
T20 |
847 |
830 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148113326 |
0 |
2415 |
T1 |
534696 |
534214 |
0 |
3 |
T2 |
239318 |
238240 |
0 |
3 |
T4 |
77521 |
5978 |
0 |
3 |
T5 |
93580 |
93510 |
0 |
3 |
T6 |
2124 |
2087 |
0 |
3 |
T7 |
2345 |
2092 |
0 |
3 |
T17 |
1715 |
1472 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1549 |
1308 |
0 |
3 |
T20 |
847 |
830 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148113326 |
0 |
2415 |
T1 |
534696 |
534214 |
0 |
3 |
T2 |
239318 |
238240 |
0 |
3 |
T4 |
77521 |
5978 |
0 |
3 |
T5 |
93580 |
93510 |
0 |
3 |
T6 |
2124 |
2087 |
0 |
3 |
T7 |
2345 |
2092 |
0 |
3 |
T17 |
1715 |
1472 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1549 |
1308 |
0 |
3 |
T20 |
847 |
830 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148113326 |
0 |
2415 |
T1 |
534696 |
534214 |
0 |
3 |
T2 |
239318 |
238240 |
0 |
3 |
T4 |
77521 |
5978 |
0 |
3 |
T5 |
93580 |
93510 |
0 |
3 |
T6 |
2124 |
2087 |
0 |
3 |
T7 |
2345 |
2092 |
0 |
3 |
T17 |
1715 |
1472 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1549 |
1308 |
0 |
3 |
T20 |
847 |
830 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148113326 |
0 |
2415 |
T1 |
534696 |
534214 |
0 |
3 |
T2 |
239318 |
238240 |
0 |
3 |
T4 |
77521 |
5978 |
0 |
3 |
T5 |
93580 |
93510 |
0 |
3 |
T6 |
2124 |
2087 |
0 |
3 |
T7 |
2345 |
2092 |
0 |
3 |
T17 |
1715 |
1472 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1549 |
1308 |
0 |
3 |
T20 |
847 |
830 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
148120370 |
0 |
0 |
T1 |
534696 |
534218 |
0 |
0 |
T2 |
239318 |
238241 |
0 |
0 |
T4 |
77521 |
6017 |
0 |
0 |
T5 |
93580 |
93513 |
0 |
0 |
T6 |
2124 |
2090 |
0 |
0 |
T7 |
2345 |
2095 |
0 |
0 |
T17 |
1715 |
1475 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1549 |
1311 |
0 |
0 |
T20 |
847 |
833 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482554611 |
0 |
2415 |
T1 |
231155 |
230946 |
0 |
3 |
T2 |
470236 |
468274 |
0 |
3 |
T4 |
78303 |
6038 |
0 |
3 |
T5 |
182956 |
182812 |
0 |
3 |
T6 |
8853 |
8709 |
0 |
3 |
T7 |
2392 |
2134 |
0 |
3 |
T17 |
1613 |
1370 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1565 |
1322 |
0 |
3 |
T20 |
6515 |
6400 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
32747 |
0 |
0 |
T1 |
231155 |
865 |
0 |
0 |
T2 |
470236 |
341 |
0 |
0 |
T4 |
78303 |
13 |
0 |
0 |
T5 |
182956 |
1 |
0 |
0 |
T6 |
8853 |
17 |
0 |
0 |
T7 |
2392 |
22 |
0 |
0 |
T17 |
1613 |
8 |
0 |
0 |
T18 |
1313 |
3 |
0 |
0 |
T19 |
1565 |
3 |
0 |
0 |
T20 |
6515 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482554611 |
0 |
2415 |
T1 |
231155 |
230946 |
0 |
3 |
T2 |
470236 |
468274 |
0 |
3 |
T4 |
78303 |
6038 |
0 |
3 |
T5 |
182956 |
182812 |
0 |
3 |
T6 |
8853 |
8709 |
0 |
3 |
T7 |
2392 |
2134 |
0 |
3 |
T17 |
1613 |
1370 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1565 |
1322 |
0 |
3 |
T20 |
6515 |
6400 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
32631 |
0 |
0 |
T1 |
231155 |
875 |
0 |
0 |
T2 |
470236 |
360 |
0 |
0 |
T4 |
78303 |
13 |
0 |
0 |
T5 |
182956 |
1 |
0 |
0 |
T6 |
8853 |
11 |
0 |
0 |
T7 |
2392 |
11 |
0 |
0 |
T17 |
1613 |
12 |
0 |
0 |
T18 |
1313 |
3 |
0 |
0 |
T19 |
1565 |
3 |
0 |
0 |
T20 |
6515 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482554611 |
0 |
2415 |
T1 |
231155 |
230946 |
0 |
3 |
T2 |
470236 |
468274 |
0 |
3 |
T4 |
78303 |
6038 |
0 |
3 |
T5 |
182956 |
182812 |
0 |
3 |
T6 |
8853 |
8709 |
0 |
3 |
T7 |
2392 |
2134 |
0 |
3 |
T17 |
1613 |
1370 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1565 |
1322 |
0 |
3 |
T20 |
6515 |
6400 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
33119 |
0 |
0 |
T1 |
231155 |
875 |
0 |
0 |
T2 |
470236 |
350 |
0 |
0 |
T4 |
78303 |
13 |
0 |
0 |
T5 |
182956 |
1 |
0 |
0 |
T6 |
8853 |
25 |
0 |
0 |
T7 |
2392 |
16 |
0 |
0 |
T17 |
1613 |
4 |
0 |
0 |
T18 |
1313 |
3 |
0 |
0 |
T19 |
1565 |
3 |
0 |
0 |
T20 |
6515 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T6,T7 |
1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482554611 |
0 |
2415 |
T1 |
231155 |
230946 |
0 |
3 |
T2 |
470236 |
468274 |
0 |
3 |
T4 |
78303 |
6038 |
0 |
3 |
T5 |
182956 |
182812 |
0 |
3 |
T6 |
8853 |
8709 |
0 |
3 |
T7 |
2392 |
2134 |
0 |
3 |
T17 |
1613 |
1370 |
0 |
3 |
T18 |
1313 |
1227 |
0 |
3 |
T19 |
1565 |
1322 |
0 |
3 |
T20 |
6515 |
6400 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
32871 |
0 |
0 |
T1 |
231155 |
854 |
0 |
0 |
T2 |
470236 |
333 |
0 |
0 |
T4 |
78303 |
13 |
0 |
0 |
T5 |
182956 |
1 |
0 |
0 |
T6 |
8853 |
13 |
0 |
0 |
T7 |
2392 |
16 |
0 |
0 |
T17 |
1613 |
12 |
0 |
0 |
T18 |
1313 |
3 |
0 |
0 |
T19 |
1565 |
3 |
0 |
0 |
T20 |
6515 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
482561555 |
0 |
0 |
T1 |
231155 |
230947 |
0 |
0 |
T2 |
470236 |
468276 |
0 |
0 |
T4 |
78303 |
6077 |
0 |
0 |
T5 |
182956 |
182815 |
0 |
0 |
T6 |
8853 |
8712 |
0 |
0 |
T7 |
2392 |
2137 |
0 |
0 |
T17 |
1613 |
1373 |
0 |
0 |
T18 |
1313 |
1230 |
0 |
0 |
T19 |
1565 |
1325 |
0 |
0 |
T20 |
6515 |
6403 |
0 |
0 |