Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	150493108	147982592	0	0
AllClkBypReqTrue_A	150493108	135475	0	0
IoClkBypReqFalse_A	150493108	147903029	0	2415
IoClkBypReqTrue_A	150493108	210432	0	0
LcClkBypAckFalse_A	150493108	147992525	0	0
LcClkBypAckTrue_A	150493108	125542	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	147982592	0	0
T1	534696	533741	0	0
T2	239318	238089	0	0
T4	77521	6004	0	0
T5	93580	93512	0	0
T6	2124	1631	0	0
T7	2345	1695	0	0
T17	1715	1474	0	0
T18	1313	1229	0	0
T19	1549	1310	0	0
T20	847	832	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	135475	0	0
T1	534696	4758	0	0
T2	239318	1521	0	0
T3	0	1287	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	458	0	0
T7	2345	399	0	0
T10	0	1471	0	0
T11	0	1051	0	0
T13	0	581	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T61	0	262	0	0
T108	0	538	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	147903029	0	2415
T1	534696	533534	0	3
T2	239318	238043	0	3
T4	77521	5978	0	3
T5	93580	93510	0	3
T6	2124	1586	0	3
T7	2345	1634	0	3
T17	1715	1472	0	3
T18	1313	1227	0	3
T19	1549	1308	0	3
T20	847	830	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	210432	0	0
T1	534696	6804	0	0
T2	239318	1966	0	0
T3	0	2017	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	501	0	0
T7	2345	458	0	0
T10	0	2140	0	0
T11	0	1478	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T61	0	357	0	0
T62	0	28	0	0
T109	0	40	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	147992525	0	0
T1	534696	533812	0	0
T2	239318	238144	0	0
T4	77521	6004	0	0
T5	93580	93512	0	0
T6	2124	1838	0	0
T7	2345	1771	0	0
T17	1715	1474	0	0
T18	1313	1229	0	0
T19	1549	1310	0	0
T20	847	832	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	125542	0	0
T1	534696	4049	0	0
T2	239318	969	0	0
T3	0	1120	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	251	0	0
T7	2345	323	0	0
T10	0	1290	0	0
T11	0	907	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T61	0	170	0	0
T62	0	21	0	0
T109	0	32	0	0