Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1948086516	15323	0	0
TransStop_A	1948086516	7928	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1948086516	15323	0	0
T1	924620	537	0	0
T2	1880944	153	0	0
T3	0	262	0	0
T4	313216	0	0	0
T5	731824	0	0	0
T6	35412	0	0	0
T7	9572	0	0	0
T10	0	286	0	0
T11	0	76	0	0
T12	0	10	0	0
T17	6456	0	0	0
T18	5256	0	0	0
T19	6260	0	0	0
T20	26060	0	0	0
T22	0	16	0	0
T58	0	4	0	0
T63	0	4	0	0
T110	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1948086516	7928	0	0
T1	924620	304	0	0
T2	1880944	80	0	0
T3	0	124	0	0
T4	313216	0	0	0
T5	731824	0	0	0
T6	35412	0	0	0
T7	9572	0	0	0
T10	0	115	0	0
T11	0	51	0	0
T12	0	2	0	0
T17	6456	0	0	0
T18	5256	0	0	0
T19	6260	0	0	0
T20	26060	0	0	0
T22	0	6	0	0
T58	0	4	0	0
T63	0	4	0	0
T110	0	4	0	0
T111	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	487021629	3810	0	0
TransStop_A	487021629	1994	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021629	3810	0	0
T1	231155	129	0	0
T2	470236	39	0	0
T3	0	55	0	0
T4	78304	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2393	0	0	0
T10	0	78	0	0
T11	0	20	0	0
T12	0	2	0	0
T17	1614	0	0	0
T18	1314	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	4	0	0
T58	0	1	0	0
T63	0	1	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021629	1994	0	0
T1	231155	66	0	0
T2	470236	22	0	0
T3	0	29	0	0
T4	78304	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2393	0	0	0
T10	0	32	0	0
T11	0	13	0	0
T17	1614	0	0	0
T18	1314	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	1	0	0
T58	0	1	0	0
T63	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	487021629	3835	0	0
TransStop_A	487021629	1969	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021629	3835	0	0
T1	231155	135	0	0
T2	470236	34	0	0
T3	0	72	0	0
T4	78304	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2393	0	0	0
T10	0	72	0	0
T11	0	20	0	0
T12	0	2	0	0
T17	1614	0	0	0
T18	1314	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	5	0	0
T58	0	1	0	0
T63	0	1	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021629	1969	0	0
T1	231155	79	0	0
T2	470236	19	0	0
T3	0	36	0	0
T4	78304	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2393	0	0	0
T10	0	28	0	0
T11	0	14	0	0
T17	1614	0	0	0
T18	1314	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	2	0	0
T58	0	1	0	0
T63	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	487021629	3877	0	0
TransStop_A	487021629	1984	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021629	3877	0	0
T1	231155	135	0	0
T2	470236	43	0	0
T3	0	67	0	0
T4	78304	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2393	0	0	0
T10	0	73	0	0
T11	0	18	0	0
T12	0	3	0	0
T17	1614	0	0	0
T18	1314	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	5	0	0
T58	0	1	0	0
T63	0	1	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021629	1984	0	0
T1	231155	77	0	0
T2	470236	22	0	0
T3	0	28	0	0
T4	78304	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2393	0	0	0
T10	0	26	0	0
T11	0	12	0	0
T12	0	1	0	0
T17	1614	0	0	0
T18	1314	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	2	0	0
T58	0	1	0	0
T63	0	1	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	487021629	3801	0	0
TransStop_A	487021629	1981	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021629	3801	0	0
T1	231155	138	0	0
T2	470236	37	0	0
T3	0	68	0	0
T4	78304	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2393	0	0	0
T10	0	63	0	0
T11	0	18	0	0
T12	0	3	0	0
T17	1614	0	0	0
T18	1314	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	2	0	0
T58	0	1	0	0
T63	0	1	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021629	1981	0	0
T1	231155	82	0	0
T2	470236	17	0	0
T3	0	31	0	0
T4	78304	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2393	0	0	0
T10	0	29	0	0
T11	0	12	0	0
T12	0	1	0	0
T17	1614	0	0	0
T18	1314	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	1	0	0
T58	0	1	0	0
T63	0	1	0	0
T110	0	1	0	0