SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 300986216 | 296240740 | 0 | 0 |
gen_flops.OutputDelay_A | 300986216 | 296226652 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
T20 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 300986216 | 296240740 | 0 | 0 |
T1 | 1069392 | 1068436 | 0 | 0 |
T2 | 478636 | 476482 | 0 | 0 |
T4 | 155042 | 12034 | 0 | 0 |
T5 | 187160 | 187026 | 0 | 0 |
T6 | 4248 | 4180 | 0 | 0 |
T7 | 4690 | 4190 | 0 | 0 |
T17 | 3430 | 2950 | 0 | 0 |
T18 | 2626 | 2460 | 0 | 0 |
T19 | 3098 | 2622 | 0 | 0 |
T20 | 1694 | 1666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 300986216 | 296226652 | 0 | 4830 |
T1 | 1069392 | 1068428 | 0 | 6 |
T2 | 478636 | 476480 | 0 | 6 |
T4 | 155042 | 11956 | 0 | 6 |
T5 | 187160 | 187020 | 0 | 6 |
T6 | 4248 | 4174 | 0 | 6 |
T7 | 4690 | 4184 | 0 | 6 |
T17 | 3430 | 2944 | 0 | 6 |
T18 | 2626 | 2454 | 0 | 6 |
T19 | 3098 | 2616 | 0 | 6 |
T20 | 1694 | 1660 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 150493108 | 148120370 | 0 | 0 |
gen_flops.OutputDelay_A | 150493108 | 148113326 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 150493108 | 148120370 | 0 | 0 |
T1 | 534696 | 534218 | 0 | 0 |
T2 | 239318 | 238241 | 0 | 0 |
T4 | 77521 | 6017 | 0 | 0 |
T5 | 93580 | 93513 | 0 | 0 |
T6 | 2124 | 2090 | 0 | 0 |
T7 | 2345 | 2095 | 0 | 0 |
T17 | 1715 | 1475 | 0 | 0 |
T18 | 1313 | 1230 | 0 | 0 |
T19 | 1549 | 1311 | 0 | 0 |
T20 | 847 | 833 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 150493108 | 148113326 | 0 | 2415 |
T1 | 534696 | 534214 | 0 | 3 |
T2 | 239318 | 238240 | 0 | 3 |
T4 | 77521 | 5978 | 0 | 3 |
T5 | 93580 | 93510 | 0 | 3 |
T6 | 2124 | 2087 | 0 | 3 |
T7 | 2345 | 2092 | 0 | 3 |
T17 | 1715 | 1472 | 0 | 3 |
T18 | 1313 | 1227 | 0 | 3 |
T19 | 1549 | 1308 | 0 | 3 |
T20 | 847 | 830 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 150493108 | 148120370 | 0 | 0 |
gen_flops.OutputDelay_A | 150493108 | 148113326 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 150493108 | 148120370 | 0 | 0 |
T1 | 534696 | 534218 | 0 | 0 |
T2 | 239318 | 238241 | 0 | 0 |
T4 | 77521 | 6017 | 0 | 0 |
T5 | 93580 | 93513 | 0 | 0 |
T6 | 2124 | 2090 | 0 | 0 |
T7 | 2345 | 2095 | 0 | 0 |
T17 | 1715 | 1475 | 0 | 0 |
T18 | 1313 | 1230 | 0 | 0 |
T19 | 1549 | 1311 | 0 | 0 |
T20 | 847 | 833 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 150493108 | 148113326 | 0 | 2415 |
T1 | 534696 | 534214 | 0 | 3 |
T2 | 239318 | 238240 | 0 | 3 |
T4 | 77521 | 5978 | 0 | 3 |
T5 | 93580 | 93510 | 0 | 3 |
T6 | 2124 | 2087 | 0 | 3 |
T7 | 2345 | 2092 | 0 | 3 |
T17 | 1715 | 1472 | 0 | 3 |
T18 | 1313 | 1227 | 0 | 3 |
T19 | 1549 | 1308 | 0 | 3 |
T20 | 847 | 830 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |