Unified Coverage Report :: Module :: prim_subreg_shadow

Module : prim_subreg_shadow

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg_shadow

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Module : prim_subreg_shadow

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T46,T47,T48
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T46,T47,T48
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T46,T47,T48

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T48

---

Branch Coverage for Module : prim_subreg_shadow

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Module : prim_subreg_shadow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	10100	10100	0	0
MubiIsNotYetSupported_A	2147483647	2147483647	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10100	10100	0	0
T1	10	10	0	0
T2	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T6	10	10	0	0
T7	10	10	0	0
T17	10	10	0	0
T18	10	10	0	0
T19	10	10	0	0
T20	10	10	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2437556	2435844	0	0
T2	2893812	2883788	0	0
T4	445076	38410	0	0
T5	1049650	1048820	0	0
T6	57968	57240	0	0
T7	15452	14042	0	0
T17	10070	8732	0	0
T18	8260	7770	0	0
T19	9708	8370	0	0
T20	41118	40466	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T46,T47,T48
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T47,T48,T49
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T47,T48,T49

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T48

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	459466602	455041681	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459466602	455041681	0	0
T1	219137	218937	0	0
T2	429532	428032	0	0
T4	75169	5833	0	0
T5	146833	146698	0	0
T6	8498	8363	0	0
T7	2297	2052	0	0
T17	1557	1326	0	0
T18	1260	1180	0	0
T19	1502	1271	0	0
T20	6255	6147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T47,T48,T49
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T47,T48,T49
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T46,T47,T48
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T46,T47,T48

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T48

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	459466602	455041681	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459466602	455041681	0	0
T1	219137	218937	0	0
T2	429532	428032	0	0
T4	75169	5833	0	0
T5	146833	146698	0	0
T6	8498	8363	0	0
T7	2297	2052	0	0
T17	1557	1326	0	0
T18	1260	1180	0	0
T19	1502	1271	0	0
T20	6255	6147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T47,T49,T50
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T49
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T47,T49,T50
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T49,T51,T52
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T49,T51,T52

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T49

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	228902074	227805708	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228902074	227805708	0	0
T1	109631	109573	0	0
T2	214473	214127	0	0
T4	20987	2918	0	0
T5	73397	73349	0	0
T6	4924	4910	0	0
T7	1260	1205	0	0
T17	718	663	0	0
T18	618	590	0	0
T19	691	636	0	0
T20	3108	3073	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T47,T49,T51
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T49
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T47,T49,T51
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T49,T51,T52
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T49,T51,T52

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T49

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	228902074	227805708	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228902074	227805708	0	0
T1	109631	109573	0	0
T2	214473	214127	0	0
T4	20987	2918	0	0
T5	73397	73349	0	0
T6	4924	4910	0	0
T7	1260	1205	0	0
T17	718	663	0	0
T18	618	590	0	0
T19	691	636	0	0
T20	3108	3073	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T47,T49,T51
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T47,T49,T51
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T47,T49,T53
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T47,T49,T53

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T48

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	114450406	113902334	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114450406	113902334	0	0
T1	548158	547868	0	0
T2	107236	107063	0	0
T4	10494	1460	0	0
T5	36699	36675	0	0
T6	2460	2453	0	0
T7	629	601	0	0
T17	359	331	0	0
T18	309	295	0	0
T19	345	317	0	0
T20	1554	1537	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T47,T49,T54
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T47,T49,T54
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T47,T48,T49
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T47,T48,T49

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T48

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	114450406	113902334	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114450406	113902334	0	0
T1	548158	547868	0	0
T2	107236	107063	0	0
T4	10494	1460	0	0
T5	36699	36675	0	0
T6	2460	2453	0	0
T7	629	601	0	0
T17	359	331	0	0
T18	309	295	0	0
T19	345	317	0	0
T20	1554	1537	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T47,T50,T55
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T47,T48,T49
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T47,T50,T55
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T46,T47,T48
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T46,T47,T48

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T47,T48,T49

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	489667687	485023528	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489667687	485023528	0	0
T1	231155	230947	0	0
T2	470236	468276	0	0
T4	78303	6077	0	0
T5	182956	182815	0	0
T6	8853	8712	0	0
T7	2392	2137	0	0
T17	1613	1373	0	0
T18	1313	1230	0	0
T19	1565	1325	0	0
T20	6515	6403	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T47,T50,T56
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T47,T50,T56
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T47,T48,T53
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T47,T48,T53

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T48

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	489667687	485023528	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489667687	485023528	0	0
T1	231155	230947	0	0
T2	470236	468276	0	0
T4	78303	6077	0	0
T5	182956	182815	0	0
T6	8853	8712	0	0
T7	2392	2137	0	0
T17	1613	1373	0	0
T18	1313	1230	0	0
T19	1565	1325	0	0
T20	6515	6403	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T46,T47,T49
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T49
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T46,T47,T49
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T46,T47,T53
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T46,T47,T53

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T49

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	235039008	232794885	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235039008	232794885	0	0
T1	110697	110597	0	0
T2	225429	224396	0	0
T4	37585	2917	0	0
T5	84940	84873	0	0
T6	4249	4182	0	0
T7	1148	1026	0	0
T17	788	673	0	0
T18	630	590	0	0
T19	751	636	0	0
T20	3127	3073	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T46,T47,T49
1	1	Covered	T1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T4,T2

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T46,T47,T49
1	1	1	Covered	T1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Covered	T1,T4,T5
1	1	0	1	Covered	T46,T53,T57
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T46,T53,T57

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T46,T47,T48

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1010	1010	0	0
MubiIsNotYetSupported_A	235039008	232794885	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235039008	232794885	0	0
T1	110697	110597	0	0
T2	225429	224396	0	0
T4	37585	2917	0	0
T5	84940	84873	0	0
T6	4249	4182	0	0
T7	1148	1026	0	0
T17	788	673	0	0
T18	630	590	0	0
T19	751	636	0	0
T20	3127	3073	0	0