Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	150493108	17846220	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	17846220	0	60
T1	534696	688658	0	0
T2	239318	44981	0	0
T3	0	66230	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	0	0	0
T7	2345	0	0	0
T10	0	32021	0	0
T11	0	832765	0	0
T12	0	32414	0	1
T13	0	7803	0	0
T14	0	7687	0	1
T15	0	0	0	1
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T23	0	734	0	1
T24	0	825	0	0
T44	0	0	0	1
T45	0	0	0	1
T79	0	0	0	1
T112	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1