Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	151379385	4907338	0	0
clk_enables_rd_A	151379385	35913	0	0
clk_hints_rd_A	151379385	32297	0	0
extclk_ctrl_rd_A	151379385	42133	0	0
extclk_ctrl_regwen_rd_A	151379385	30804	0	0
jitter_enable_rd_A	151379385	46771	0	0
jitter_regwen_rd_A	151379385	34245	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151379385	4907338	0	0
T1	534696	187983	0	0
T2	239318	86748	0	0
T3	0	156581	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	0	0	0
T7	2345	0	0	0
T10	0	80828	0	0
T11	0	101445	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T39	0	29947	0	0
T40	0	95849	0	0
T42	0	61300	0	0
T59	0	146943	0	0
T60	0	119100	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151379385	35913	0	0
T11	214702	0	0	0
T12	0	6	0	0
T16	0	11	0	0
T22	175348	0	0	0
T24	0	4	0	0
T30	1022	0	0	0
T39	0	1089	0	0
T42	0	2276	0	0
T58	2027	2	0	0
T59	0	3203	0	0
T61	2182	0	0	0
T62	1016	0	0	0
T63	1713	1	0	0
T110	1899	0	0	0
T129	0	5	0	0
T130	0	15	0	0
T131	919	0	0	0
T132	1871	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151379385	32297	0	0
T11	214702	0	0	0
T12	0	7	0	0
T16	0	9	0	0
T22	175348	0	0	0
T24	0	3	0	0
T30	1022	0	0	0
T39	0	1027	0	0
T42	0	2116	0	0
T58	2027	1	0	0
T59	0	2762	0	0
T61	2182	0	0	0
T62	1016	0	0	0
T63	1713	0	0	0
T110	1899	0	0	0
T130	0	8	0	0
T131	919	0	0	0
T132	1871	0	0	0
T133	0	4	0	0
T134	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151379385	42133	0	0
T2	239318	0	0	0
T4	77521	0	0	0
T5	93580	0	0	0
T6	2124	82	0	0
T7	2345	51	0	0
T16	0	42	0	0
T17	1715	0	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T21	18296	0	0	0
T65	0	24	0	0
T74	0	42	0	0
T75	0	42	0	0
T109	0	5	0	0
T135	0	15	0	0
T136	0	84	0	0
T137	0	47	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151379385	30804	0	0
T14	46616	0	0	0
T15	123373	0	0	0
T31	1585	0	0	0
T39	0	1078	0	0
T42	0	2146	0	0
T59	0	2506	0	0
T65	15483	9	0	0
T106	0	71	0	0
T107	0	24	0	0
T135	2051	0	0	0
T138	0	21	0	0
T139	0	2575	0	0
T140	0	2462	0	0
T141	0	35	0	0
T142	1859	0	0	0
T143	914	0	0	0
T144	2048	0	0	0
T145	1096	0	0	0
T146	2866	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151379385	46771	0	0
T11	214702	0	0	0
T12	0	98	0	0
T16	0	180	0	0
T22	175348	0	0	0
T24	0	116	0	0
T30	1022	0	0	0
T39	0	1387	0	0
T42	0	3426	0	0
T58	2027	103	0	0
T59	0	3225	0	0
T61	2182	0	0	0
T62	1016	0	0	0
T63	1713	108	0	0
T110	1899	0	0	0
T129	0	136	0	0
T130	0	276	0	0
T131	919	0	0	0
T132	1871	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151379385	34245	0	0
T39	101395	1172	0	0
T40	190727	0	0	0
T41	1836	0	0	0
T42	203421	2505	0	0
T43	1609	0	0	0
T44	24584	0	0	0
T45	35430	0	0	0
T59	451679	2897	0	0
T139	0	3114	0	0
T140	0	2630	0	0
T147	0	3732	0	0
T148	0	1452	0	0
T149	0	6675	0	0
T150	0	1468	0	0
T151	0	1136	0	0
T152	1690	0	0	0
T153	25143	0	0	0