Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 3 | 50.00 |
Logical | 6 | 3 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T6,T7 |
1 | 1 | Covered | T1,T6,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T6,T7 |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
19259566 |
0 |
0 |
T1 |
6565738 |
958842 |
0 |
0 |
T2 |
3840086 |
189926 |
0 |
0 |
T3 |
0 |
2364 |
0 |
0 |
T4 |
997748 |
152 |
0 |
0 |
T5 |
1460625 |
463 |
0 |
0 |
T6 |
50224 |
538 |
0 |
0 |
T7 |
31176 |
138 |
0 |
0 |
T10 |
0 |
1799 |
0 |
0 |
T11 |
0 |
1598 |
0 |
0 |
T12 |
0 |
79 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
33 |
0 |
0 |
T15 |
0 |
51 |
0 |
0 |
T17 |
22185 |
93 |
0 |
0 |
T18 |
17260 |
75 |
0 |
0 |
T19 |
20344 |
83 |
0 |
0 |
T20 |
29029 |
387 |
0 |
0 |
T21 |
0 |
27 |
0 |
0 |
T22 |
0 |
140 |
0 |
0 |
T23 |
0 |
113 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
138427 |
0 |
0 |
T1 |
2437556 |
3834 |
0 |
0 |
T2 |
2893812 |
1554 |
0 |
0 |
T3 |
0 |
2259 |
0 |
0 |
T4 |
445076 |
108 |
0 |
0 |
T5 |
1049650 |
160 |
0 |
0 |
T6 |
57968 |
0 |
0 |
0 |
T7 |
15452 |
0 |
0 |
0 |
T10 |
0 |
1774 |
0 |
0 |
T11 |
0 |
1513 |
0 |
0 |
T12 |
0 |
79 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
33 |
0 |
0 |
T15 |
0 |
51 |
0 |
0 |
T17 |
10070 |
0 |
0 |
0 |
T18 |
8260 |
0 |
0 |
0 |
T19 |
9708 |
0 |
0 |
0 |
T20 |
41118 |
0 |
0 |
0 |
T21 |
0 |
26 |
0 |
0 |
T22 |
0 |
140 |
0 |
0 |
T23 |
0 |
113 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T6,T7 |
1 | 1 | Covered | T1,T6,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456926071 |
3856647 |
0 |
0 |
T1 |
219137 |
241554 |
0 |
0 |
T2 |
429532 |
47605 |
0 |
0 |
T4 |
75169 |
11 |
0 |
0 |
T5 |
146833 |
73 |
0 |
0 |
T6 |
8498 |
136 |
0 |
0 |
T7 |
2297 |
35 |
0 |
0 |
T17 |
1557 |
24 |
0 |
0 |
T18 |
1260 |
19 |
0 |
0 |
T19 |
1502 |
21 |
0 |
0 |
T20 |
6255 |
98 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17405924 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T6,T7 |
1 | 1 | Covered | T1,T6,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
227675037 |
3856526 |
0 |
0 |
T1 |
109631 |
241554 |
0 |
0 |
T2 |
214473 |
47604 |
0 |
0 |
T4 |
20987 |
11 |
0 |
0 |
T5 |
73397 |
73 |
0 |
0 |
T6 |
4924 |
136 |
0 |
0 |
T7 |
1260 |
35 |
0 |
0 |
T17 |
718 |
24 |
0 |
0 |
T18 |
618 |
19 |
0 |
0 |
T19 |
691 |
21 |
0 |
0 |
T20 |
3108 |
98 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17405924 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T6,T7 |
1 | 1 | Covered | T1,T6,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113836900 |
3680603 |
0 |
0 |
T1 |
548158 |
230113 |
0 |
0 |
T2 |
107236 |
45439 |
0 |
0 |
T4 |
10494 |
11 |
0 |
0 |
T5 |
36699 |
73 |
0 |
0 |
T6 |
2460 |
130 |
0 |
0 |
T7 |
629 |
33 |
0 |
0 |
T17 |
359 |
22 |
0 |
0 |
T18 |
309 |
18 |
0 |
0 |
T19 |
345 |
20 |
0 |
0 |
T20 |
1554 |
93 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17405924 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T6,T7 |
1 | 1 | Covered | T1,T6,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
3860858 |
0 |
0 |
T1 |
231155 |
241667 |
0 |
0 |
T2 |
470236 |
47689 |
0 |
0 |
T4 |
78303 |
11 |
0 |
0 |
T5 |
182956 |
84 |
0 |
0 |
T6 |
8853 |
136 |
0 |
0 |
T7 |
2392 |
35 |
0 |
0 |
T17 |
1613 |
23 |
0 |
0 |
T18 |
1313 |
19 |
0 |
0 |
T19 |
1565 |
21 |
0 |
0 |
T20 |
6515 |
98 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17405924 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T6,T7 |
1 | 1 | Covered | T1,T6,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T6,T7 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T6,T7 |
EVEN |
0 |
- |
Covered |
T1,T6,T7 |
ODD |
- |
1 |
Covered |
T1,T6,T7 |
ODD |
- |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233768724 |
3860759 |
0 |
0 |
T1 |
110697 |
241647 |
0 |
0 |
T2 |
225429 |
47686 |
0 |
0 |
T4 |
37585 |
11 |
0 |
0 |
T5 |
84940 |
83 |
0 |
0 |
T6 |
4249 |
136 |
0 |
0 |
T7 |
1148 |
35 |
0 |
0 |
T17 |
788 |
24 |
0 |
0 |
T18 |
630 |
19 |
0 |
0 |
T19 |
751 |
21 |
0 |
0 |
T20 |
3127 |
98 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17405924 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151379385 |
26049 |
0 |
0 |
T1 |
534696 |
690 |
0 |
0 |
T2 |
239318 |
298 |
0 |
0 |
T3 |
0 |
436 |
0 |
0 |
T4 |
77521 |
24 |
0 |
0 |
T5 |
93580 |
32 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
346 |
0 |
0 |
T11 |
0 |
282 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459466602 |
24926 |
0 |
0 |
T1 |
219137 |
666 |
0 |
0 |
T2 |
429532 |
291 |
0 |
0 |
T3 |
0 |
415 |
0 |
0 |
T4 |
75169 |
24 |
0 |
0 |
T5 |
146833 |
32 |
0 |
0 |
T6 |
8498 |
0 |
0 |
0 |
T7 |
2297 |
0 |
0 |
0 |
T10 |
0 |
341 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T17 |
1557 |
0 |
0 |
0 |
T18 |
1260 |
0 |
0 |
0 |
T19 |
1502 |
0 |
0 |
0 |
T20 |
6255 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151379385 |
26049 |
0 |
0 |
T1 |
534696 |
690 |
0 |
0 |
T2 |
239318 |
298 |
0 |
0 |
T3 |
0 |
436 |
0 |
0 |
T4 |
77521 |
24 |
0 |
0 |
T5 |
93580 |
32 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
346 |
0 |
0 |
T11 |
0 |
282 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
228902074 |
24924 |
0 |
0 |
T1 |
109631 |
666 |
0 |
0 |
T2 |
214473 |
291 |
0 |
0 |
T3 |
0 |
415 |
0 |
0 |
T4 |
20987 |
24 |
0 |
0 |
T5 |
73397 |
32 |
0 |
0 |
T6 |
4924 |
0 |
0 |
0 |
T7 |
1260 |
0 |
0 |
0 |
T10 |
0 |
341 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T17 |
718 |
0 |
0 |
0 |
T18 |
618 |
0 |
0 |
0 |
T19 |
691 |
0 |
0 |
0 |
T20 |
3108 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151379385 |
26049 |
0 |
0 |
T1 |
534696 |
690 |
0 |
0 |
T2 |
239318 |
298 |
0 |
0 |
T3 |
0 |
436 |
0 |
0 |
T4 |
77521 |
24 |
0 |
0 |
T5 |
93580 |
32 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
346 |
0 |
0 |
T11 |
0 |
282 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114450406 |
24888 |
0 |
0 |
T1 |
548158 |
666 |
0 |
0 |
T2 |
107236 |
291 |
0 |
0 |
T3 |
0 |
415 |
0 |
0 |
T4 |
10494 |
24 |
0 |
0 |
T5 |
36699 |
32 |
0 |
0 |
T6 |
2460 |
0 |
0 |
0 |
T7 |
629 |
0 |
0 |
0 |
T10 |
0 |
341 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T17 |
359 |
0 |
0 |
0 |
T18 |
309 |
0 |
0 |
0 |
T19 |
345 |
0 |
0 |
0 |
T20 |
1554 |
0 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151379385 |
26049 |
0 |
0 |
T1 |
534696 |
690 |
0 |
0 |
T2 |
239318 |
298 |
0 |
0 |
T3 |
0 |
436 |
0 |
0 |
T4 |
77521 |
24 |
0 |
0 |
T5 |
93580 |
32 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
346 |
0 |
0 |
T11 |
0 |
282 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489667687 |
24926 |
0 |
0 |
T1 |
231155 |
666 |
0 |
0 |
T2 |
470236 |
291 |
0 |
0 |
T3 |
0 |
415 |
0 |
0 |
T4 |
78303 |
24 |
0 |
0 |
T5 |
182956 |
32 |
0 |
0 |
T6 |
8853 |
0 |
0 |
0 |
T7 |
2392 |
0 |
0 |
0 |
T10 |
0 |
341 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T17 |
1613 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1565 |
0 |
0 |
0 |
T20 |
6515 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T5,T2 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T5,T2 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151379385 |
25554 |
0 |
0 |
T1 |
534696 |
690 |
0 |
0 |
T2 |
239318 |
298 |
0 |
0 |
T3 |
0 |
436 |
0 |
0 |
T4 |
77521 |
12 |
0 |
0 |
T5 |
93580 |
32 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
346 |
0 |
0 |
T11 |
0 |
282 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
235039008 |
24340 |
0 |
0 |
T1 |
110697 |
666 |
0 |
0 |
T2 |
225429 |
291 |
0 |
0 |
T3 |
0 |
415 |
0 |
0 |
T4 |
37585 |
12 |
0 |
0 |
T5 |
84940 |
32 |
0 |
0 |
T6 |
4249 |
0 |
0 |
0 |
T7 |
1148 |
0 |
0 |
0 |
T10 |
0 |
341 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T17 |
788 |
0 |
0 |
0 |
T18 |
630 |
0 |
0 |
0 |
T19 |
751 |
0 |
0 |
0 |
T20 |
3127 |
0 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T23 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
3099 |
0 |
0 |
T1 |
534696 |
141 |
0 |
0 |
T2 |
239318 |
17 |
0 |
0 |
T3 |
0 |
35 |
0 |
0 |
T4 |
77521 |
0 |
0 |
0 |
T5 |
93580 |
0 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
36 |
0 |
0 |
T12 |
0 |
17 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
14 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T23 |
0 |
9 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456926071 |
3099 |
0 |
0 |
T1 |
219137 |
141 |
0 |
0 |
T2 |
429532 |
17 |
0 |
0 |
T3 |
0 |
35 |
0 |
0 |
T4 |
75169 |
0 |
0 |
0 |
T5 |
146833 |
0 |
0 |
0 |
T6 |
8498 |
0 |
0 |
0 |
T7 |
2297 |
0 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
36 |
0 |
0 |
T12 |
0 |
17 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
14 |
0 |
0 |
T17 |
1557 |
0 |
0 |
0 |
T18 |
1260 |
0 |
0 |
0 |
T19 |
1502 |
0 |
0 |
0 |
T20 |
6255 |
0 |
0 |
0 |
T23 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
3167 |
0 |
0 |
T1 |
534696 |
70 |
0 |
0 |
T2 |
239318 |
20 |
0 |
0 |
T3 |
0 |
22 |
0 |
0 |
T4 |
77521 |
0 |
0 |
0 |
T5 |
93580 |
0 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
15 |
0 |
0 |
T11 |
0 |
54 |
0 |
0 |
T12 |
0 |
18 |
0 |
0 |
T13 |
0 |
9 |
0 |
0 |
T14 |
0 |
7 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T23 |
0 |
3 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
227675037 |
3167 |
0 |
0 |
T1 |
109631 |
70 |
0 |
0 |
T2 |
214473 |
20 |
0 |
0 |
T3 |
0 |
22 |
0 |
0 |
T4 |
20987 |
0 |
0 |
0 |
T5 |
73397 |
0 |
0 |
0 |
T6 |
4924 |
0 |
0 |
0 |
T7 |
1260 |
0 |
0 |
0 |
T10 |
0 |
15 |
0 |
0 |
T11 |
0 |
54 |
0 |
0 |
T12 |
0 |
18 |
0 |
0 |
T13 |
0 |
9 |
0 |
0 |
T14 |
0 |
7 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T17 |
718 |
0 |
0 |
0 |
T18 |
618 |
0 |
0 |
0 |
T19 |
691 |
0 |
0 |
0 |
T20 |
3108 |
0 |
0 |
0 |
T23 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
2905 |
0 |
0 |
T1 |
534696 |
124 |
0 |
0 |
T2 |
239318 |
13 |
0 |
0 |
T3 |
0 |
41 |
0 |
0 |
T4 |
77521 |
0 |
0 |
0 |
T5 |
93580 |
0 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
0 |
22 |
0 |
0 |
T12 |
0 |
31 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
13 |
0 |
0 |
T15 |
0 |
7 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113836900 |
2905 |
0 |
0 |
T1 |
548158 |
124 |
0 |
0 |
T2 |
107236 |
13 |
0 |
0 |
T3 |
0 |
41 |
0 |
0 |
T4 |
10494 |
0 |
0 |
0 |
T5 |
36699 |
0 |
0 |
0 |
T6 |
2460 |
0 |
0 |
0 |
T7 |
629 |
0 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
0 |
22 |
0 |
0 |
T12 |
0 |
31 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
13 |
0 |
0 |
T15 |
0 |
7 |
0 |
0 |
T17 |
359 |
0 |
0 |
0 |
T18 |
309 |
0 |
0 |
0 |
T19 |
345 |
0 |
0 |
0 |
T20 |
1554 |
0 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
2551 |
0 |
0 |
T1 |
534696 |
84 |
0 |
0 |
T2 |
239318 |
19 |
0 |
0 |
T3 |
0 |
45 |
0 |
0 |
T4 |
77521 |
0 |
0 |
0 |
T5 |
93580 |
0 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
22 |
0 |
0 |
T11 |
0 |
22 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
7 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T15 |
0 |
4 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487021190 |
2551 |
0 |
0 |
T1 |
231155 |
84 |
0 |
0 |
T2 |
470236 |
19 |
0 |
0 |
T3 |
0 |
45 |
0 |
0 |
T4 |
78303 |
0 |
0 |
0 |
T5 |
182956 |
0 |
0 |
0 |
T6 |
8853 |
0 |
0 |
0 |
T7 |
2392 |
0 |
0 |
0 |
T10 |
0 |
22 |
0 |
0 |
T11 |
0 |
22 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
7 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T15 |
0 |
4 |
0 |
0 |
T17 |
1613 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1565 |
0 |
0 |
0 |
T20 |
6515 |
0 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T6,T7 |
0 |
Covered |
T1,T6,T7 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
150493108 |
2701 |
0 |
0 |
T1 |
534696 |
85 |
0 |
0 |
T2 |
239318 |
30 |
0 |
0 |
T3 |
0 |
41 |
0 |
0 |
T4 |
77521 |
0 |
0 |
0 |
T5 |
93580 |
0 |
0 |
0 |
T6 |
2124 |
0 |
0 |
0 |
T7 |
2345 |
0 |
0 |
0 |
T10 |
0 |
7 |
0 |
0 |
T11 |
0 |
54 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T15 |
0 |
23 |
0 |
0 |
T17 |
1715 |
0 |
0 |
0 |
T18 |
1313 |
0 |
0 |
0 |
T19 |
1549 |
0 |
0 |
0 |
T20 |
847 |
0 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233768724 |
2701 |
0 |
0 |
T1 |
110697 |
85 |
0 |
0 |
T2 |
225429 |
30 |
0 |
0 |
T3 |
0 |
41 |
0 |
0 |
T4 |
37585 |
0 |
0 |
0 |
T5 |
84940 |
0 |
0 |
0 |
T6 |
4249 |
0 |
0 |
0 |
T7 |
1148 |
0 |
0 |
0 |
T10 |
0 |
7 |
0 |
0 |
T11 |
0 |
54 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T15 |
0 |
23 |
0 |
0 |
T17 |
788 |
0 |
0 |
0 |
T18 |
630 |
0 |
0 |
0 |
T19 |
751 |
0 |
0 |
0 |
T20 |
3127 |
0 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |