Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	456926531	4506	0	0
g_div2.Div2Whole_A	456926531	5181	0	0
g_div4.Div4Stepped_A	227675429	4438	0	0
g_div4.Div4Whole_A	227675429	4978	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926531	4506	0	0
T1	219137	131	0	0
T2	429532	33	0	0
T3	0	58	0	0
T4	75169	0	0	0
T5	146834	0	0	0
T6	8498	10	0	0
T7	2297	11	0	0
T10	0	51	0	0
T11	0	32	0	0
T17	1557	0	0	0
T18	1261	0	0	0
T19	1503	0	0	0
T20	6255	0	0	0
T61	0	7	0	0
T62	0	1	0	0
T109	0	1	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926531	5181	0	0
T1	219137	135	0	0
T2	429532	36	0	0
T3	0	62	0	0
T4	75169	0	0	0
T5	146834	0	0	0
T6	8498	10	0	0
T7	2297	11	0	0
T10	0	63	0	0
T11	0	47	0	0
T17	1557	0	0	0
T18	1261	0	0	0
T19	1503	0	0	0
T20	6255	0	0	0
T61	0	10	0	0
T62	0	1	0	0
T109	0	1	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675429	4438	0	0
T1	109631	131	0	0
T2	214473	30	0	0
T3	0	58	0	0
T4	20987	0	0	0
T5	73398	0	0	0
T6	4924	10	0	0
T7	1261	10	0	0
T10	0	51	0	0
T11	0	29	0	0
T17	719	0	0	0
T18	618	0	0	0
T19	691	0	0	0
T20	3109	0	0	0
T61	0	6	0	0
T62	0	1	0	0
T109	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675429	4978	0	0
T1	109631	135	0	0
T2	214473	36	0	0
T3	0	62	0	0
T4	20987	0	0	0
T5	73398	0	0	0
T6	4924	10	0	0
T7	1261	9	0	0
T10	0	63	0	0
T11	0	37	0	0
T17	719	0	0	0
T18	618	0	0	0
T19	691	0	0	0
T20	3109	0	0	0
T61	0	10	0	0
T62	0	1	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	456926531	4506	0	0
g_div2.Div2Whole_A	456926531	5181	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926531	4506	0	0
T1	219137	131	0	0
T2	429532	33	0	0
T3	0	58	0	0
T4	75169	0	0	0
T5	146834	0	0	0
T6	8498	10	0	0
T7	2297	11	0	0
T10	0	51	0	0
T11	0	32	0	0
T17	1557	0	0	0
T18	1261	0	0	0
T19	1503	0	0	0
T20	6255	0	0	0
T61	0	7	0	0
T62	0	1	0	0
T109	0	1	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926531	5181	0	0
T1	219137	135	0	0
T2	429532	36	0	0
T3	0	62	0	0
T4	75169	0	0	0
T5	146834	0	0	0
T6	8498	10	0	0
T7	2297	11	0	0
T10	0	63	0	0
T11	0	47	0	0
T17	1557	0	0	0
T18	1261	0	0	0
T19	1503	0	0	0
T20	6255	0	0	0
T61	0	10	0	0
T62	0	1	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	227675429	4438	0	0
g_div4.Div4Whole_A	227675429	4978	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675429	4438	0	0
T1	109631	131	0	0
T2	214473	30	0	0
T3	0	58	0	0
T4	20987	0	0	0
T5	73398	0	0	0
T6	4924	10	0	0
T7	1261	10	0	0
T10	0	51	0	0
T11	0	29	0	0
T17	719	0	0	0
T18	618	0	0	0
T19	691	0	0	0
T20	3109	0	0	0
T61	0	6	0	0
T62	0	1	0	0
T109	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675429	4978	0	0
T1	109631	135	0	0
T2	214473	36	0	0
T3	0	62	0	0
T4	20987	0	0	0
T5	73398	0	0	0
T6	4924	10	0	0
T7	1261	9	0	0
T10	0	63	0	0
T11	0	37	0	0
T17	719	0	0	0
T18	618	0	0	0
T19	691	0	0	0
T20	3109	0	0	0
T61	0	10	0	0
T62	0	1	0	0
T109	0	1	0	0