Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	451479324	482	0	0
StatusRise_A	451479324	482	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451479324	482	0	0
T2	717954	0	0	0
T3	947337	0	0	0
T5	280740	0	0	0
T10	506580	0	0	0
T17	5145	9	0	0
T18	3939	0	0	0
T19	4647	0	0	0
T20	2541	0	0	0
T21	54888	0	0	0
T25	4425	0	0	0
T30	0	10	0	0
T31	0	15	0	0
T145	0	12	0	0
T154	0	9	0	0
T155	0	14	0	0
T156	0	14	0	0
T157	0	6	0	0
T158	0	6	0	0
T159	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451479324	482	0	0
T2	717954	0	0	0
T3	947337	0	0	0
T5	280740	0	0	0
T10	506580	0	0	0
T17	5145	9	0	0
T18	3939	0	0	0
T19	4647	0	0	0
T20	2541	0	0	0
T21	54888	0	0	0
T25	4425	0	0	0
T30	0	10	0	0
T31	0	15	0	0
T145	0	12	0	0
T154	0	9	0	0
T155	0	14	0	0
T156	0	14	0	0
T157	0	6	0	0
T158	0	6	0	0
T159	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	150493108	156	0	0
StatusRise_A	150493108	156	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	156	0	0
T2	239318	0	0	0
T3	315779	0	0	0
T5	93580	0	0	0
T10	168860	0	0	0
T17	1715	2	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	3	0	0
T31	0	5	0	0
T145	0	5	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	156	0	0
T2	239318	0	0	0
T3	315779	0	0	0
T5	93580	0	0	0
T10	168860	0	0	0
T17	1715	2	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	3	0	0
T31	0	5	0	0
T145	0	5	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	150493108	169	0	0
StatusRise_A	150493108	169	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	169	0	0
T2	239318	0	0	0
T3	315779	0	0	0
T5	93580	0	0	0
T10	168860	0	0	0
T17	1715	4	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	169	0	0
T2	239318	0	0	0
T3	315779	0	0	0
T5	93580	0	0	0
T10	168860	0	0	0
T17	1715	4	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	150493108	157	0	0
StatusRise_A	150493108	157	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	157	0	0
T2	239318	0	0	0
T3	315779	0	0	0
T5	93580	0	0	0
T10	168860	0	0	0
T17	1715	3	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	3	0	0
T31	0	3	0	0
T145	0	4	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150493108	157	0	0
T2	239318	0	0	0
T3	315779	0	0	0
T5	93580	0	0	0
T10	168860	0	0	0
T17	1715	3	0	0
T18	1313	0	0	0
T19	1549	0	0	0
T20	847	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	3	0	0
T31	0	3	0	0
T145	0	4	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0