Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	49113	0	0
CgEnOn_A	2147483647	39889	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49113	0	0
T1	1912243	538	0	0
T2	4989228	316	0	0
T3	2552777	55	0	0
T4	457447	39	0	0
T5	1854872	3	0	0
T6	55543	3	0	0
T7	14902	3	0	0
T10	3428301	83	0	0
T17	17240	37	0	0
T18	14130	3	0	0
T19	16658	3	0	0
T20	70286	3	0	0
T21	75744	0	0	0
T22	0	4	0	0
T25	6814	0	0	0
T30	0	23	0	0
T31	0	35	0	0
T58	0	1	0	0
T145	0	15	0	0
T154	0	15	0	0
T155	0	25	0	0
T156	0	25	0	0
T157	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39889	0	0
T1	1912243	1034	0	0
T2	4989228	498	0	0
T3	2552777	911	0	0
T4	457447	0	0	0
T5	1854872	0	0	0
T6	55543	0	0	0
T7	14902	0	0	0
T10	3428301	555	0	0
T11	0	388	0	0
T17	17240	50	0	0
T18	14130	0	0	0
T19	16658	0	0	0
T20	70286	0	0	0
T21	75744	0	0	0
T22	0	51	0	0
T25	6814	0	0	0
T30	0	41	0	0
T31	0	48	0	0
T58	0	8	0	0
T63	0	8	0	0
T131	0	15	0	0
T145	0	29	0	0
T154	0	24	0	0
T155	0	39	0	0
T156	0	39	0	0
T157	0	16	0	0
T158	0	8	0	0
T159	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Unreachable
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	227675037	174	0	0
CgEnOn_A	227675037	174	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675037	174	0	0
T2	214473	1	0	0
T3	616994	0	0	0
T5	73397	0	0	0
T10	144640	1	0	0
T17	718	4	0	0
T18	618	0	0	0
T19	691	0	0	0
T20	3108	0	0	0
T21	5123	0	0	0
T25	696	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675037	174	0	0
T2	214473	1	0	0
T3	616994	0	0	0
T5	73397	0	0	0
T10	144640	1	0	0
T17	718	4	0	0
T18	618	0	0	0
T19	691	0	0	0
T20	3108	0	0	0
T21	5123	0	0	0
T25	696	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Unreachable
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113836900	174	0	0
CgEnOn_A	113836900	174	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113836900	174	0	0
T2	107236	1	0	0
T3	308496	0	0	0
T5	36699	0	0	0
T10	723197	1	0	0
T17	359	4	0	0
T18	309	0	0	0
T19	345	0	0	0
T20	1554	0	0	0
T21	2561	0	0	0
T25	348	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113836900	174	0	0
T2	107236	1	0	0
T3	308496	0	0	0
T5	36699	0	0	0
T10	723197	1	0	0
T17	359	4	0	0
T18	309	0	0	0
T19	345	0	0	0
T20	1554	0	0	0
T21	2561	0	0	0
T25	348	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Unreachable
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113836900	174	0	0
CgEnOn_A	113836900	174	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113836900	174	0	0
T2	107236	1	0	0
T3	308496	0	0	0
T5	36699	0	0	0
T10	723197	1	0	0
T17	359	4	0	0
T18	309	0	0	0
T19	345	0	0	0
T20	1554	0	0	0
T21	2561	0	0	0
T25	348	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113836900	174	0	0
T2	107236	1	0	0
T3	308496	0	0	0
T5	36699	0	0	0
T10	723197	1	0	0
T17	359	4	0	0
T18	309	0	0	0
T19	345	0	0	0
T20	1554	0	0	0
T21	2561	0	0	0
T25	348	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Unreachable
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113836900	174	0	0
CgEnOn_A	113836900	174	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113836900	174	0	0
T2	107236	1	0	0
T3	308496	0	0	0
T5	36699	0	0	0
T10	723197	1	0	0
T17	359	4	0	0
T18	309	0	0	0
T19	345	0	0	0
T20	1554	0	0	0
T21	2561	0	0	0
T25	348	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113836900	174	0	0
T2	107236	1	0	0
T3	308496	0	0	0
T5	36699	0	0	0
T10	723197	1	0	0
T17	359	4	0	0
T18	309	0	0	0
T19	345	0	0	0
T20	1554	0	0	0
T21	2561	0	0	0
T25	348	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Unreachable
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	456926071	174	0	0
CgEnOn_A	456926071	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926071	174	0	0
T2	429532	1	0	0
T3	123371	0	0	0
T5	146833	0	0	0
T10	289507	1	0	0
T17	1557	4	0	0
T18	1260	0	0	0
T19	1502	0	0	0
T20	6255	0	0	0
T21	17564	0	0	0
T25	1416	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926071	170	0	0
T2	429532	0	0	0
T3	123371	0	0	0
T5	146833	0	0	0
T10	289507	1	0	0
T17	1557	4	0	0
T18	1260	0	0	0
T19	1502	0	0	0
T20	6255	0	0	0
T21	17564	0	0	0
T25	1416	0	0	0
T30	0	4	0	0
T31	0	7	0	0
T145	0	3	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Unreachable
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487021190	162	0	0
CgEnOn_A	487021190	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	162	0	0
T2	470236	0	0	0
T3	130555	0	0	0
T5	182956	0	0	0
T10	332454	0	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	3	0	0
T31	0	5	0	0
T145	0	5	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	159	0	0
T2	470236	0	0	0
T3	130555	0	0	0
T5	182956	0	0	0
T10	332454	0	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	3	0	0
T31	0	5	0	0
T145	0	5	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Unreachable
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487021190	162	0	0
CgEnOn_A	487021190	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	162	0	0
T2	470236	0	0	0
T3	130555	0	0	0
T5	182956	0	0	0
T10	332454	0	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	3	0	0
T31	0	5	0	0
T145	0	5	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	159	0	0
T2	470236	0	0	0
T3	130555	0	0	0
T5	182956	0	0	0
T10	332454	0	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T21	18296	0	0	0
T25	1475	0	0	0
T30	0	3	0	0
T31	0	5	0	0
T145	0	5	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Unreachable
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233768724	158	0	0
CgEnOn_A	233768724	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233768724	158	0	0
T2	225429	0	0	0
T3	625814	0	0	0
T5	84940	0	0	0
T10	159655	0	0	0
T17	788	3	0	0
T18	630	0	0	0
T19	751	0	0	0
T20	3127	0	0	0
T21	8782	0	0	0
T25	708	0	0	0
T30	0	3	0	0
T31	0	3	0	0
T145	0	4	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233768724	157	0	0
T2	225429	0	0	0
T3	625814	0	0	0
T5	84940	0	0	0
T10	159655	0	0	0
T17	788	3	0	0
T18	630	0	0	0
T19	751	0	0	0
T20	3127	0	0	0
T21	8782	0	0	0
T25	708	0	0	0
T30	0	3	0	0
T31	0	3	0	0
T145	0	4	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T31
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113836900	7957	0	0
CgEnOn_A	113836900	5659	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113836900	7957	0	0
T1	548158	138	0	0
T2	107236	94	0	0
T4	10494	13	0	0
T5	36699	1	0	0
T6	2460	1	0	0
T7	629	1	0	0
T17	359	5	0	0
T18	309	1	0	0
T19	345	1	0	0
T20	1554	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113836900	5659	0	0
T1	548158	127	0	0
T2	107236	89	0	0
T3	0	167	0	0
T4	10494	0	0	0
T5	36699	0	0	0
T6	2460	0	0	0
T7	629	0	0	0
T10	0	62	0	0
T11	0	77	0	0
T17	359	4	0	0
T18	309	0	0	0
T19	345	0	0	0
T20	1554	0	0	0
T22	0	8	0	0
T58	0	1	0	0
T63	0	1	0	0
T131	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T31
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	227675037	7942	0	0
CgEnOn_A	227675037	5644	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675037	7942	0	0
T1	109631	136	0	0
T2	214473	90	0	0
T4	20987	13	0	0
T5	73397	1	0	0
T6	4924	1	0	0
T7	1260	1	0	0
T17	718	5	0	0
T18	618	1	0	0
T19	691	1	0	0
T20	3108	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227675037	5644	0	0
T1	109631	125	0	0
T2	214473	85	0	0
T3	0	168	0	0
T4	20987	0	0	0
T5	73397	0	0	0
T6	4924	0	0	0
T7	1260	0	0	0
T10	0	71	0	0
T11	0	78	0	0
T17	718	4	0	0
T18	618	0	0	0
T19	691	0	0	0
T20	3108	0	0	0
T22	0	9	0	0
T58	0	1	0	0
T63	0	1	0	0
T131	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T31
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	456926071	7943	0	0
CgEnOn_A	456926071	5641	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926071	7943	0	0
T1	219137	135	0	0
T2	429532	88	0	0
T4	75169	13	0	0
T5	146833	1	0	0
T6	8498	1	0	0
T7	2297	1	0	0
T17	1557	5	0	0
T18	1260	1	0	0
T19	1502	1	0	0
T20	6255	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926071	5641	0	0
T1	219137	124	0	0
T2	429532	82	0	0
T3	0	153	0	0
T4	75169	0	0	0
T5	146833	0	0	0
T6	8498	0	0	0
T7	2297	0	0	0
T10	0	65	0	0
T11	0	80	0	0
T17	1557	4	0	0
T18	1260	0	0	0
T19	1502	0	0	0
T20	6255	0	0	0
T22	0	9	0	0
T58	0	1	0	0
T63	0	1	0	0
T131	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T31
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233768724	7948	0	0
CgEnOn_A	233768724	5645	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233768724	7948	0	0
T1	110697	132	0	0
T2	225429	91	0	0
T4	37585	13	0	0
T5	84940	1	0	0
T6	4249	1	0	0
T7	1148	1	0	0
T17	788	4	0	0
T18	630	1	0	0
T19	751	1	0	0
T20	3127	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233768724	5645	0	0
T1	110697	121	0	0
T2	225429	85	0	0
T3	0	161	0	0
T4	37585	0	0	0
T5	84940	0	0	0
T6	4249	0	0	0
T7	1148	0	0	0
T10	0	66	0	0
T11	0	77	0	0
T17	788	3	0	0
T18	630	0	0	0
T19	751	0	0	0
T20	3127	0	0	0
T22	0	9	0	0
T58	0	1	0	0
T63	0	1	0	0
T131	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487021190	3972	0	0
CgEnOn_A	487021190	3969	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	3972	0	0
T1	231155	129	0	0
T2	470236	39	0	0
T3	0	55	0	0
T4	78303	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2392	0	0	0
T10	0	78	0	0
T11	0	20	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	4	0	0
T30	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	3969	0	0
T1	231155	129	0	0
T2	470236	39	0	0
T3	0	55	0	0
T4	78303	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2392	0	0	0
T10	0	78	0	0
T11	0	20	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	4	0	0
T30	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487021190	3997	0	0
CgEnOn_A	487021190	3994	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	3997	0	0
T1	231155	135	0	0
T2	470236	34	0	0
T3	0	72	0	0
T4	78303	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2392	0	0	0
T10	0	72	0	0
T11	0	20	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	5	0	0
T30	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	3994	0	0
T1	231155	135	0	0
T2	470236	34	0	0
T3	0	72	0	0
T4	78303	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2392	0	0	0
T10	0	72	0	0
T11	0	20	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	5	0	0
T30	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487021190	4039	0	0
CgEnOn_A	487021190	4036	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	4039	0	0
T1	231155	135	0	0
T2	470236	43	0	0
T3	0	67	0	0
T4	78303	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2392	0	0	0
T10	0	73	0	0
T11	0	18	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	5	0	0
T30	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	4036	0	0
T1	231155	135	0	0
T2	470236	43	0	0
T3	0	67	0	0
T4	78303	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2392	0	0	0
T10	0	73	0	0
T11	0	18	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	5	0	0
T30	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487021190	3963	0	0
CgEnOn_A	487021190	3960	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	3963	0	0
T1	231155	138	0	0
T2	470236	37	0	0
T3	0	68	0	0
T4	78303	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2392	0	0	0
T10	0	63	0	0
T11	0	18	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	2	0	0
T30	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487021190	3960	0	0
T1	231155	138	0	0
T2	470236	37	0	0
T3	0	68	0	0
T4	78303	0	0	0
T5	182956	0	0	0
T6	8853	0	0	0
T7	2392	0	0	0
T10	0	63	0	0
T11	0	18	0	0
T17	1613	2	0	0
T18	1313	0	0	0
T19	1565	0	0	0
T20	6515	0	0	0
T22	0	2	0	0
T30	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0