Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	577034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3154788

1

T6

3

T7

8

T26

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	921041	1			T7	11		T26	20		T27	6
values[0x0]	1293583	1			T6	14		T7	14		T26	8
values[0x1]	1517198	1			T6	9		T7	9		T26	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	325713	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3406109

1

T6

5

T7

11

T26

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15144	1			T29	1		T2	2		T3	1
valid_sources[0x01]	15193	1			T2	2		T4	18		T3	2
valid_sources[0x02]	14613	1			T2	3		T12	243		T66	3
valid_sources[0x03]	14295	1			T27	1		T3	1		T12	188
valid_sources[0x04]	17575	1			T35	14		T2	2		T4	4
valid_sources[0x05]	14947	1			T2	1		T3	1		T45	1
valid_sources[0x06]	14864	1			T2	2		T4	3		T3	1
valid_sources[0x07]	14288	1			T2	3		T18	1		T3	1
valid_sources[0x08]	13704	1			T18	1		T3	7		T12	207
valid_sources[0x09]	14164	1			T4	9		T3	3		T34	1
valid_sources[0x0a]	14452	1			T26	1		T2	1		T3	2
valid_sources[0x0b]	14911	1			T2	1		T3	1		T34	1
valid_sources[0x0c]	14385	1			T2	1		T18	2		T48	1
valid_sources[0x0d]	14163	1			T2	2		T18	2		T23	8
valid_sources[0x0e]	14919	1			T2	2		T23	1		T3	1
valid_sources[0x0f]	15137	1			T2	3		T3	4		T82	1
valid_sources[0x10]	13404	1			T2	1		T4	3		T3	1
valid_sources[0x11]	13946	1			T31	1		T2	2		T3	2
valid_sources[0x12]	14524	1			T2	3		T24	39		T3	2
valid_sources[0x13]	14271	1			T18	1		T3	2		T34	1
valid_sources[0x14]	14247	1			T26	1		T2	3		T3	2
valid_sources[0x15]	14593	1			T6	1		T2	2		T18	2
valid_sources[0x16]	14225	1			T2	5		T18	4		T4	3
valid_sources[0x17]	13784	1			T27	1		T2	1		T3	2
valid_sources[0x18]	15266	1			T2	3		T12	203		T13	1
valid_sources[0x19]	14191	1			T2	2		T3	1		T12	170
valid_sources[0x1a]	13953	1			T2	3		T3	2		T34	3
valid_sources[0x1b]	14075	1			T2	2		T18	1		T3	1
valid_sources[0x1c]	13948	1			T2	3		T18	1		T23	3
valid_sources[0x1d]	14476	1			T2	1		T34	1		T12	227
valid_sources[0x1e]	14169	1			T2	1		T3	2		T12	231
valid_sources[0x1f]	14378	1			T2	2		T18	1		T25	14
valid_sources[0x20]	14061	1			T31	1		T2	3		T18	1
valid_sources[0x21]	13911	1			T2	2		T18	1		T3	3
valid_sources[0x22]	14931	1			T18	1		T3	1		T34	1
valid_sources[0x23]	13923	1			T2	1		T12	273		T66	1
valid_sources[0x24]	15052	1			T2	2		T3	1		T34	1
valid_sources[0x25]	15495	1			T2	3		T81	1		T12	228
valid_sources[0x26]	15079	1			T31	1		T2	3		T18	2
valid_sources[0x27]	14556	1			T2	1		T18	1		T3	1
valid_sources[0x28]	14995	1			T6	2		T2	3		T48	2
valid_sources[0x29]	14297	1			T2	1		T4	2		T3	2
valid_sources[0x2a]	13680	1			T31	1		T2	4		T4	1
valid_sources[0x2b]	15349	1			T2	2		T3	1		T34	4
valid_sources[0x2c]	15871	1			T2	2		T3	2		T12	211
valid_sources[0x2d]	13421	1			T27	1		T2	2		T3	1
valid_sources[0x2e]	14448	1			T27	1		T2	2		T34	2
valid_sources[0x2f]	13447	1			T3	2		T34	2		T12	239
valid_sources[0x30]	15129	1			T27	1		T29	1		T3	5
valid_sources[0x31]	14038	1			T2	3		T48	2		T3	1
valid_sources[0x32]	14012	1			T2	6		T18	1		T3	3
valid_sources[0x33]	15580	1			T29	1		T2	1		T23	4
valid_sources[0x34]	14804	1			T2	3		T3	3		T11	7
valid_sources[0x35]	14266	1			T29	2		T2	2		T18	5
valid_sources[0x36]	13636	1			T18	2		T3	10		T34	2
valid_sources[0x37]	14394	1			T31	1		T2	1		T48	1
valid_sources[0x38]	15333	1			T2	1		T3	5		T34	1
valid_sources[0x39]	14600	1			T2	4		T80	11		T3	2
valid_sources[0x3a]	15170	1			T2	3		T3	1		T12	246
valid_sources[0x3b]	15669	1			T29	1		T30	52		T2	3
valid_sources[0x3c]	13032	1			T2	3		T3	3		T11	6
valid_sources[0x3d]	15289	1			T2	3		T18	1		T3	2
valid_sources[0x3e]	15430	1			T2	1		T3	1		T34	3
valid_sources[0x3f]	15523	1			T6	2		T2	4		T3	4
valid_sources[0x40]	14103	1			T26	1		T2	1		T3	1
valid_sources[0x41]	13668	1			T2	2		T3	1		T34	3
valid_sources[0x42]	13666	1			T2	3		T3	4		T34	4
valid_sources[0x43]	14726	1			T2	1		T18	1		T3	2
valid_sources[0x44]	14870	1			T2	2		T34	1		T12	217
valid_sources[0x45]	14051	1			T48	2		T3	4		T34	1
valid_sources[0x46]	14536	1			T6	1		T2	3		T23	3
valid_sources[0x47]	14368	1			T2	2		T18	1		T4	14
valid_sources[0x48]	15688	1			T29	2		T2	1		T34	1
valid_sources[0x49]	14880	1			T2	1		T3	3		T34	1
valid_sources[0x4a]	14353	1			T2	2		T3	1		T12	265
valid_sources[0x4b]	14622	1			T27	1		T5	20		T2	1
valid_sources[0x4c]	15052	1			T2	2		T3	1		T11	3
valid_sources[0x4d]	14449	1			T2	2		T3	2		T11	8
valid_sources[0x4e]	14931	1			T2	2		T3	3		T12	192
valid_sources[0x4f]	14067	1			T3	3		T34	2		T12	239
valid_sources[0x50]	13632	1			T35	5		T2	1		T12	230
valid_sources[0x51]	14694	1			T2	6		T18	1		T3	2
valid_sources[0x52]	14791	1			T2	2		T12	231		T13	1
valid_sources[0x53]	13705	1			T2	3		T18	1		T23	1
valid_sources[0x54]	15401	1			T4	10		T3	3		T34	1
valid_sources[0x55]	13474	1			T2	4		T34	4		T12	229
valid_sources[0x56]	14736	1			T27	1		T2	1		T3	1
valid_sources[0x57]	14024	1			T26	3		T3	5		T34	1
valid_sources[0x58]	14697	1			T2	1		T4	4		T48	1
valid_sources[0x59]	15994	1			T27	1		T2	1		T18	2
valid_sources[0x5a]	15183	1			T2	1		T4	8		T3	1
valid_sources[0x5b]	14590	1			T31	3		T2	3		T12	290
valid_sources[0x5c]	13900	1			T2	2		T3	2		T82	1
valid_sources[0x5d]	15562	1			T2	4		T34	3		T12	222
valid_sources[0x5e]	15313	1			T2	1		T19	1		T3	2
valid_sources[0x5f]	14852	1			T26	3		T29	1		T2	1
valid_sources[0x60]	13962	1			T6	4		T19	2		T3	1
valid_sources[0x61]	14346	1			T2	3		T3	4		T34	4
valid_sources[0x62]	14364	1			T2	2		T3	3		T11	3
valid_sources[0x63]	14927	1			T2	1		T45	4		T12	251
valid_sources[0x64]	13462	1			T2	1		T19	1		T3	2
valid_sources[0x65]	15230	1			T6	1		T2	4		T3	3
valid_sources[0x66]	13095	1			T2	5		T3	2		T11	2
valid_sources[0x67]	13564	1			T5	1		T2	5		T3	2
valid_sources[0x68]	14049	1			T3	1		T34	1		T12	222
valid_sources[0x69]	16709	1			T29	1		T2	3		T3	5
valid_sources[0x6a]	15118	1			T2	2		T18	2		T3	1
valid_sources[0x6b]	15228	1			T5	3		T2	4		T19	2
valid_sources[0x6c]	15397	1			T27	2		T2	1		T48	1
valid_sources[0x6d]	14708	1			T27	1		T35	30		T3	1
valid_sources[0x6e]	14196	1			T2	1		T18	2		T23	4
valid_sources[0x6f]	14243	1			T3	2		T34	2		T81	1
valid_sources[0x70]	15116	1			T2	3		T3	2		T34	2
valid_sources[0x71]	17609	1			T2	3		T18	2		T3	2
valid_sources[0x72]	14216	1			T2	4		T34	1		T12	241
valid_sources[0x73]	15689	1			T26	2		T2	1		T3	1
valid_sources[0x74]	13728	1			T2	3		T22	3		T3	1
valid_sources[0x75]	13829	1			T27	1		T35	10		T2	1
valid_sources[0x76]	13640	1			T2	2		T18	1		T23	3
valid_sources[0x77]	14599	1			T6	1		T26	2		T18	2
valid_sources[0x78]	14232	1			T2	2		T18	3		T4	8
valid_sources[0x79]	14039	1			T2	3		T3	5		T11	2
valid_sources[0x7a]	14438	1			T35	22		T2	2		T3	1
valid_sources[0x7b]	14830	1			T2	4		T3	2		T34	1
valid_sources[0x7c]	15170	1			T2	3		T3	2		T34	2
valid_sources[0x7d]	15870	1			T2	3		T48	1		T3	1
valid_sources[0x7e]	14547	1			T2	2		T3	3		T12	279
valid_sources[0x7f]	14053	1			T2	2		T3	5		T12	221
valid_sources[0x80]	13645	1			T2	1		T3	2		T34	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

798273

1

T7

3

T26

10

T27

4

values[0x0]

all_enables

biggest_size

1201616

1

T6

3

T7

4

T26

3

values[0x1]

all_enables

biggest_size

1154899

1

T7

1

T26

1

T27

1