Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T35
0	1	Covered	T6,T19,T24
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T35,T18
1	0	Covered	T8,T42,T43
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	971618821	14794	0	0
GateOpen_A	971618821	21338	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971618821	14794	0	0
T5	61115	0	0	0
T6	5311	17	0	0
T7	35225	0	0	0
T8	3033	6	0	0
T12	0	280	0	0
T15	0	105	0	0
T19	0	10	0	0
T24	0	28	0	0
T26	6438	0	0	0
T27	4015	0	0	0
T28	7073	0	0	0
T29	8463	0	0	0
T30	7930	0	0	0
T31	3693	0	0	0
T35	0	4	0	0
T45	0	4	0	0
T69	0	11	0	0
T80	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971618821	21338	0	0
T5	61115	4	0	0
T6	5311	17	0	0
T7	35225	4	0	0
T8	3033	10	0	0
T18	0	400	0	0
T26	6438	0	0	0
T27	4015	0	0	0
T28	7073	4	0	0
T29	8463	4	0	0
T30	7930	4	0	0
T31	3693	4	0	0
T35	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T35
0	1	Covered	T6,T19,T24
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T35,T18
1	0	Covered	T8,T42,T43
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	107124546	3522	0	0
GateOpen_A	107124546	5155	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124546	3522	0	0
T5	6144	0	0	0
T6	586	4	0	0
T7	4022	0	0	0
T8	329	1	0	0
T12	0	64	0	0
T15	0	25	0	0
T19	0	2	0	0
T24	0	7	0	0
T26	707	0	0	0
T27	433	0	0	0
T28	791	0	0	0
T29	948	0	0	0
T30	900	0	0	0
T31	405	0	0	0
T35	0	1	0	0
T45	0	1	0	0
T69	0	2	0	0
T80	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124546	5155	0	0
T5	6144	1	0	0
T6	586	4	0	0
T7	4022	1	0	0
T8	329	2	0	0
T18	0	100	0	0
T26	707	0	0	0
T27	433	0	0	0
T28	791	1	0	0
T29	948	1	0	0
T30	900	1	0	0
T31	405	1	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T35
0	1	Covered	T6,T19,T24
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T35,T18
1	0	Covered	T8,T42,T43
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	214249979	3756	0	0
GateOpen_A	214249979	5389	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214249979	3756	0	0
T5	12288	0	0	0
T6	1172	4	0	0
T7	8045	0	0	0
T8	658	1	0	0
T12	0	71	0	0
T15	0	27	0	0
T19	0	2	0	0
T24	0	6	0	0
T26	1413	0	0	0
T27	866	0	0	0
T28	1582	0	0	0
T29	1895	0	0	0
T30	1800	0	0	0
T31	810	0	0	0
T35	0	1	0	0
T45	0	1	0	0
T69	0	3	0	0
T80	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214249979	5389	0	0
T5	12288	1	0	0
T6	1172	4	0	0
T7	8045	1	0	0
T8	658	2	0	0
T18	0	100	0	0
T26	1413	0	0	0
T27	866	0	0	0
T28	1582	1	0	0
T29	1895	1	0	0
T30	1800	1	0	0
T31	810	1	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T35
0	1	Covered	T6,T19,T24
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T35,T18
1	0	Covered	T8,T42,T43
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	430021626	3768	0	0
GateOpen_A	430021626	5407	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430021626	3768	0	0
T5	24615	0	0	0
T6	2369	5	0	0
T7	15438	0	0	0
T8	1367	1	0	0
T12	0	73	0	0
T15	0	26	0	0
T19	0	3	0	0
T24	0	7	0	0
T26	2879	0	0	0
T27	1811	0	0	0
T28	3133	0	0	0
T29	3747	0	0	0
T30	3487	0	0	0
T31	1652	0	0	0
T35	0	1	0	0
T45	0	1	0	0
T69	0	3	0	0
T80	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430021626	5407	0	0
T5	24615	1	0	0
T6	2369	5	0	0
T7	15438	1	0	0
T8	1367	2	0	0
T18	0	100	0	0
T26	2879	0	0	0
T27	1811	0	0	0
T28	3133	1	0	0
T29	3747	1	0	0
T30	3487	1	0	0
T31	1652	1	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T35
0	1	Covered	T6,T19,T24
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T35,T18
1	0	Covered	T8,T42,T43
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	220222670	3748	0	0
GateOpen_A	220222670	5387	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220222670	3748	0	0
T5	18068	0	0	0
T6	1184	4	0	0
T7	7720	0	0	0
T8	679	3	0	0
T12	0	72	0	0
T15	0	27	0	0
T19	0	3	0	0
T24	0	8	0	0
T26	1439	0	0	0
T27	905	0	0	0
T28	1567	0	0	0
T29	1873	0	0	0
T30	1743	0	0	0
T31	826	0	0	0
T35	0	1	0	0
T45	0	1	0	0
T69	0	3	0	0
T80	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220222670	5387	0	0
T5	18068	1	0	0
T6	1184	4	0	0
T7	7720	1	0	0
T8	679	4	0	0
T18	0	100	0	0
T26	1439	0	0	0
T27	905	0	0	0
T28	1567	1	0	0
T29	1873	1	0	0
T30	1743	1	0	0
T31	826	1	0	0
T35	0	1	0	0