Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	761896000	76196	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761896000	76196	0	0
T1	80835	109	0	0
T2	1238495	190	0	0
T3	0	48	0	0
T11	0	69	0	0
T12	0	646	0	0
T13	0	530	0	0
T14	0	293	0	0
T15	0	936	0	0
T16	0	207	0	0
T17	0	2278	0	0
T18	142025	0	0	0
T19	4470	0	0	0
T20	9185	0	0	0
T21	6400	0	0	0
T22	6975	0	0	0
T23	12805	0	0	0
T24	10520	0	0	0
T25	5230	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152379200	11216	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	11216	0	0
T1	16167	21	0	0
T2	247699	24	0	0
T3	0	8	0	0
T11	0	13	0	0
T12	0	104	0	0
T13	0	69	0	0
T14	0	44	0	0
T15	0	121	0	0
T16	0	34	0	0
T17	0	364	0	0
T18	28405	0	0	0
T19	894	0	0	0
T20	1837	0	0	0
T21	1280	0	0	0
T22	1395	0	0	0
T23	2561	0	0	0
T24	2104	0	0	0
T25	1046	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152379200	11182	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	11182	0	0
T1	16167	21	0	0
T2	247699	27	0	0
T3	0	8	0	0
T11	0	13	0	0
T12	0	102	0	0
T13	0	68	0	0
T14	0	43	0	0
T15	0	137	0	0
T16	0	32	0	0
T17	0	358	0	0
T18	28405	0	0	0
T19	894	0	0	0
T20	1837	0	0	0
T21	1280	0	0	0
T22	1395	0	0	0
T23	2561	0	0	0
T24	2104	0	0	0
T25	1046	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152379200	15292	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	15292	0	0
T1	16167	21	0	0
T2	247699	38	0	0
T3	0	9	0	0
T11	0	13	0	0
T12	0	131	0	0
T13	0	109	0	0
T14	0	58	0	0
T15	0	185	0	0
T16	0	42	0	0
T17	0	461	0	0
T18	28405	0	0	0
T19	894	0	0	0
T20	1837	0	0	0
T21	1280	0	0	0
T22	1395	0	0	0
T23	2561	0	0	0
T24	2104	0	0	0
T25	1046	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152379200	15279	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	15279	0	0
T1	16167	21	0	0
T2	247699	39	0	0
T3	0	9	0	0
T11	0	13	0	0
T12	0	127	0	0
T13	0	105	0	0
T14	0	59	0	0
T15	0	187	0	0
T16	0	42	0	0
T17	0	463	0	0
T18	28405	0	0	0
T19	894	0	0	0
T20	1837	0	0	0
T21	1280	0	0	0
T22	1395	0	0	0
T23	2561	0	0	0
T24	2104	0	0	0
T25	1046	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152379200	23227	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	23227	0	0
T1	16167	25	0	0
T2	247699	62	0	0
T3	0	14	0	0
T11	0	17	0	0
T12	0	182	0	0
T13	0	179	0	0
T14	0	89	0	0
T15	0	306	0	0
T16	0	57	0	0
T17	0	632	0	0
T18	28405	0	0	0
T19	894	0	0	0
T20	1837	0	0	0
T21	1280	0	0	0
T22	1395	0	0	0
T23	2561	0	0	0
T24	2104	0	0	0
T25	1046	0	0	0