Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T18,T4,T34

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	152379200	149966752	0	0
AllClkBypReqTrue_A	152379200	148731	0	0
IoClkBypReqFalse_A	152379200	149881269	0	2415
IoClkBypReqTrue_A	152379200	229592	0	0
LcClkBypAckFalse_A	152379200	149981314	0	0
LcClkBypAckTrue_A	152379200	134169	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	149966752	0	0
T5	36888	36792	0	0
T6	1282	1193	0	0
T7	1447	1319	0	0
T8	1444	1290	0	0
T26	1439	1364	0	0
T27	1867	1622	0	0
T28	946	874	0	0
T29	1054	988	0	0
T30	2107	1922	0	0
T31	1720	1430	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	148731	0	0
T5	36888	0	0	0
T7	1447	117	0	0
T8	1444	0	0	0
T21	0	55	0	0
T22	0	34	0	0
T23	0	382	0	0
T26	1439	0	0	0
T27	1867	63	0	0
T28	946	30	0	0
T29	1054	0	0	0
T30	2107	127	0	0
T31	1720	120	0	0
T35	1985	0	0	0
T48	0	149	0	0
T81	0	8	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	149881269	0	2415
T5	36888	36790	0	3
T6	1282	1191	0	3
T7	1447	1434	0	3
T8	1444	1288	0	3
T26	1439	1362	0	3
T27	1867	1683	0	3
T28	946	858	0	3
T29	1054	916	0	3
T30	2107	2047	0	3
T31	1720	1397	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	229592	0	0
T1	16167	0	0	0
T2	247699	0	0	0
T5	36888	0	0	0
T12	0	5107	0	0
T18	28405	0	0	0
T19	894	0	0	0
T21	0	160	0	0
T22	0	45	0	0
T23	0	647	0	0
T28	946	44	0	0
T29	1054	70	0	0
T30	2107	0	0	0
T31	1720	151	0	0
T35	1985	0	0	0
T48	0	193	0	0
T67	0	257	0	0
T82	0	209	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	149981314	0	0
T5	36888	36792	0	0
T6	1282	1193	0	0
T7	1447	1436	0	0
T8	1444	1290	0	0
T26	1439	1364	0	0
T27	1867	1685	0	0
T28	946	865	0	0
T29	1054	953	0	0
T30	2107	2049	0	0
T31	1720	1480	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	134169	0	0
T1	16167	0	0	0
T2	247699	0	0	0
T5	36888	0	0	0
T12	0	3321	0	0
T15	0	604	0	0
T18	28405	0	0	0
T19	894	0	0	0
T21	0	67	0	0
T23	0	374	0	0
T28	946	39	0	0
T29	1054	35	0	0
T30	2107	0	0	0
T31	1720	70	0	0
T35	1985	0	0	0
T48	0	123	0	0
T67	0	40	0	0
T82	0	128	0	0