Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1834050120	16372	0	0
TransStop_A	1834050120	8432	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1834050120	16372	0	0
T1	808404	0	0	0
T2	990800	0	0	0
T5	150564	0	0	0
T12	0	364	0	0
T15	0	17	0	0
T16	0	21	0	0
T20	0	18	0	0
T25	0	5	0	0
T26	11996	11	0	0
T27	7548	0	0	0
T28	13056	0	0	0
T29	15612	0	0	0
T30	14532	0	0	0
T31	6884	0	0	0
T35	8448	4	0	0
T45	0	4	0	0
T66	0	36	0	0
T106	0	15	0	0
T107	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1834050120	8432	0	0
T1	808404	0	0	0
T2	990800	0	0	0
T5	150564	0	0	0
T12	0	216	0	0
T15	0	7	0	0
T16	0	9	0	0
T20	0	6	0	0
T25	0	3	0	0
T26	11996	5	0	0
T27	7548	0	0	0
T28	13056	0	0	0
T29	15612	0	0	0
T30	14532	0	0	0
T31	6884	0	0	0
T35	8448	4	0	0
T45	0	4	0	0
T66	0	17	0	0
T106	0	9	0	0
T107	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	458512530	4082	0	0
TransStop_A	458512530	2104	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512530	4082	0	0
T1	202101	0	0	0
T2	247700	0	0	0
T5	37641	0	0	0
T12	0	84	0	0
T15	0	4	0	0
T20	0	3	0	0
T25	0	1	0	0
T26	2999	3	0	0
T27	1887	0	0	0
T28	3264	0	0	0
T29	3903	0	0	0
T30	3633	0	0	0
T31	1721	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	11	0	0
T106	0	4	0	0
T107	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512530	2104	0	0
T1	202101	0	0	0
T2	247700	0	0	0
T5	37641	0	0	0
T12	0	54	0	0
T15	0	1	0	0
T20	0	2	0	0
T25	0	1	0	0
T26	2999	1	0	0
T27	1887	0	0	0
T28	3264	0	0	0
T29	3903	0	0	0
T30	3633	0	0	0
T31	1721	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	5	0	0
T106	0	2	0	0
T107	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	458512530	4090	0	0
TransStop_A	458512530	2107	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512530	4090	0	0
T1	202101	0	0	0
T2	247700	0	0	0
T5	37641	0	0	0
T12	0	88	0	0
T15	0	5	0	0
T16	0	21	0	0
T20	0	2	0	0
T26	2999	3	0	0
T27	1887	0	0	0
T28	3264	0	0	0
T29	3903	0	0	0
T30	3633	0	0	0
T31	1721	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	13	0	0
T106	0	4	0	0
T107	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512530	2107	0	0
T1	202101	0	0	0
T2	247700	0	0	0
T5	37641	0	0	0
T12	0	56	0	0
T15	0	2	0	0
T16	0	9	0	0
T20	0	1	0	0
T26	2999	1	0	0
T27	1887	0	0	0
T28	3264	0	0	0
T29	3903	0	0	0
T30	3633	0	0	0
T31	1721	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	6	0	0
T106	0	2	0	0
T107	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	458512530	4158	0	0
TransStop_A	458512530	2164	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512530	4158	0	0
T1	202101	0	0	0
T2	247700	0	0	0
T5	37641	0	0	0
T12	0	102	0	0
T15	0	5	0	0
T20	0	7	0	0
T25	0	2	0	0
T26	2999	2	0	0
T27	1887	0	0	0
T28	3264	0	0	0
T29	3903	0	0	0
T30	3633	0	0	0
T31	1721	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	5	0	0
T106	0	3	0	0
T107	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512530	2164	0	0
T1	202101	0	0	0
T2	247700	0	0	0
T5	37641	0	0	0
T12	0	56	0	0
T15	0	2	0	0
T20	0	2	0	0
T25	0	1	0	0
T26	2999	2	0	0
T27	1887	0	0	0
T28	3264	0	0	0
T29	3903	0	0	0
T30	3633	0	0	0
T31	1721	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	3	0	0
T106	0	3	0	0
T107	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	458512530	4042	0	0
TransStop_A	458512530	2057	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512530	4042	0	0
T1	202101	0	0	0
T2	247700	0	0	0
T5	37641	0	0	0
T12	0	90	0	0
T15	0	3	0	0
T20	0	6	0	0
T25	0	2	0	0
T26	2999	3	0	0
T27	1887	0	0	0
T28	3264	0	0	0
T29	3903	0	0	0
T30	3633	0	0	0
T31	1721	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	7	0	0
T106	0	4	0	0
T107	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512530	2057	0	0
T1	202101	0	0	0
T2	247700	0	0	0
T5	37641	0	0	0
T12	0	50	0	0
T15	0	2	0	0
T20	0	1	0	0
T25	0	1	0	0
T26	2999	1	0	0
T27	1887	0	0	0
T28	3264	0	0	0
T29	3903	0	0	0
T30	3633	0	0	0
T31	1721	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	3	0	0
T106	0	2	0	0
T107	0	1	0	0