Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	923832	0	0
SrcPulseCheck_M	2147483647	920681	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	923832
T1	751728	445
T2	1149164	582
T3	0	568
T4	0	40
T5	142151	138
T11	0	239
T12	0	5055
T13	0	224
T14	0	394
T15	0	1028
T18	122752	0
T19	17086	0
T20	27471	0
T21	21306	0
T22	6513	0
T23	114938	0
T34	0	50
T35	9435	0
T36	0	300
T50	15180	2
T51	3991	0
T52	29914	1
T55	16112	1
T58	20894	2
T112	12516	3
T113	5825	3
T114	11902	2
T115	28052	2
T116	3300	2
T117	8424	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	920681
T1	131024	445
T2	616278	582
T3	0	568
T4	0	40
T5	86328	138
T11	0	239
T12	0	5055
T13	0	224
T14	0	394
T15	0	1028
T18	75394	0
T19	5161	0
T20	9020	0
T21	6785	0
T22	3847	0
T23	29260	0
T34	0	50
T35	5508	0
T36	0	300
T50	6414	2
T51	8164	0
T52	27196	1
T55	6788	1
T58	8752	2
T112	41286	3
T113	10134	3
T114	22516	2
T115	48262	2
T116	6182	2
T117	7650	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	432854207	24554	0	0
SrcPulseCheck_M	153303526	24554	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	432854207	24554
T1	194010	32
T2	237784	42
T3	0	40
T4	0	8
T5	24614	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	28701	0
T19	4294	0
T20	6785	0
T21	5123	0
T22	1380	0
T23	27315	0
T34	0	10
T35	2027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	24554
T1	16167	32
T2	247699	42
T3	0	40
T4	0	8
T5	36888	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	10
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	432854207	30711	0	0
SrcPulseCheck_M	153303526	30722	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	432854207	30711
T1	194010	32
T2	237784	42
T3	0	40
T4	0	16
T5	24614	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28701	0
T19	4294	0
T20	6785	0
T21	5123	0
T22	1380	0
T23	27315	0
T34	0	20
T35	2027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	30722
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	30700	0	0
SrcPulseCheck_M	432854207	30711	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	30700
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	432854207	30711
T1	194010	32
T2	237784	42
T3	0	40
T4	0	16
T5	24614	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28701	0
T19	4294	0
T20	6785	0
T21	5123	0
T22	1380	0
T23	27315	0
T34	0	20
T35	2027	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	215619810	24554	0	0
SrcPulseCheck_M	153303526	24554	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	215619810	24554
T1	96986	32
T2	118852	42
T3	0	40
T4	0	8
T5	12288	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	10212	0
T19	2121	0
T20	3366	0
T21	2733	0
T22	657	0
T23	16174	0
T34	0	10
T35	946	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	24554
T1	16167	32
T2	247699	42
T3	0	40
T4	0	8
T5	36888	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	10
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	215619810	30633	0	0
SrcPulseCheck_M	153303526	30661	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	215619810	30633
T1	96986	32
T2	118852	42
T3	0	40
T4	0	16
T5	12288	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	10212	0
T19	2121	0
T20	3366	0
T21	2733	0
T22	657	0
T23	16174	0
T34	0	20
T35	946	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	30661
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	30623	0	0
SrcPulseCheck_M	215619810	30640	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	30623
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	215619810	30640
T1	96986	32
T2	118852	42
T3	0	40
T4	0	16
T5	12288	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	10212	0
T19	2121	0
T20	3366	0
T21	2733	0
T22	657	0
T23	16174	0
T34	0	20
T35	946	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	107809269	24554	0	0
SrcPulseCheck_M	153303526	24554	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	107809269	24554
T1	48493	32
T2	59426	42
T3	0	40
T4	0	8
T5	6144	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	5111	0
T19	1061	0
T20	1683	0
T21	1367	0
T22	329	0
T23	8086	0
T34	0	10
T35	473	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	24554
T1	16167	32
T2	247699	42
T3	0	40
T4	0	8
T5	36888	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	10
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	107809269	30634	0	0
SrcPulseCheck_M	153303526	30678	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	107809269	30634
T1	48493	32
T2	59426	42
T3	0	40
T4	0	16
T5	6144	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	5111	0
T19	1061	0
T20	1683	0
T21	1367	0
T22	329	0
T23	8086	0
T34	0	20
T35	473	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	30678
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	30633	0	0
SrcPulseCheck_M	107809269	30640	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	30633
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	107809269	30640
T1	48493	32
T2	59426	42
T3	0	40
T4	0	16
T5	6144	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	5111	0
T19	1061	0
T20	1683	0
T21	1367	0
T22	329	0
T23	8086	0
T34	0	20
T35	473	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	461463260	24554	0	0
SrcPulseCheck_M	153303526	24554	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	461463260	24554
T1	202100	32
T2	247699	42
T3	0	40
T4	0	8
T5	37641	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	29899	0
T19	4474	0
T20	7068	0
T21	5337	0
T22	1438	0
T23	28454	0
T34	0	10
T35	2112	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	24554
T1	16167	32
T2	247699	42
T3	0	40
T4	0	8
T5	36888	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	10
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	461463260	30552	0	0
SrcPulseCheck_M	153303526	30578	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	461463260	30552
T1	202100	32
T2	247699	42
T3	0	40
T4	0	16
T5	37641	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	29899	0
T19	4474	0
T20	7068	0
T21	5337	0
T22	1438	0
T23	28454	0
T34	0	20
T35	2112	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	30578
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	30541	0	0
SrcPulseCheck_M	461463260	30556	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	30541
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	461463260	30556
T1	202100	32
T2	247699	42
T3	0	40
T4	0	16
T5	37641	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	29899	0
T19	4474	0
T20	7068	0
T21	5337	0
T22	1438	0
T23	28454	0
T34	0	20
T35	2112	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	221638800	24134	0	0
SrcPulseCheck_M	153303526	24554	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	221638800	24134
T1	97009	32
T2	118898	42
T3	0	40
T4	0	4
T5	18067	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	14351	0
T19	2147	0
T20	3393	0
T21	2562	0
T22	690	0
T23	13658	0
T34	0	6
T35	1013	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	24554
T1	16167	32
T2	247699	42
T3	0	40
T4	0	8
T5	36888	6
T11	0	18
T12	0	252
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	10
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	221638800	30575	0	0
SrcPulseCheck_M	153303526	30698	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	221638800	30575
T1	97009	32
T2	118898	42
T3	0	40
T4	0	16
T5	18067	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	14351	0
T19	2147	0
T20	3393	0
T21	2562	0
T22	690	0
T23	13658	0
T34	0	20
T35	1013	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153303526	30698
T1	16167	32
T2	247699	42
T3	0	40
T4	0	16
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	30441	0	0
SrcPulseCheck_M	221638800	30595	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	30441
T1	16167	32
T2	247699	42
T3	0	40
T4	0	15
T5	36888	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	28405	0
T19	894	0
T20	1837	0
T21	1280	0
T22	1395	0
T23	2561	0
T34	0	20
T35	1985	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	221638800	30595
T1	97009	32
T2	118898	42
T3	0	40
T4	0	16
T5	18067	6
T11	0	18
T12	0	257
T13	0	24
T14	0	34
T18	14351	0
T19	2147	0
T20	3393	0
T21	2562	0
T22	690	0
T23	13658	0
T34	0	20
T35	1013	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T51,T54
1	0	Covered	T50,T51,T54
1	1	Covered	T51,T54,T118

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T51,T54
1	0	Covered	T51,T54,T118
1	1	Covered	T50,T51,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	33	0	0
SrcPulseCheck_M	432854207	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	33
T50	7590	2
T51	3991	2
T54	4716	2
T112	6258	1
T113	5825	1
T114	5951	2
T115	14026	1
T118	8586	2
T119	11968	3
T120	2718	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	432854207	33
T50	7434	2
T51	17417	2
T54	4716	2
T112	42914	1
T113	22367	1
T114	23804	2
T115	49869	1
T118	8325	2
T119	11968	3
T120	20075	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T53,T55
1	0	Covered	T51,T53,T55
1	1	Covered	T54,T119,T118

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T53,T55
1	0	Covered	T54,T119,T118
1	1	Covered	T51,T53,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	39	0	0
SrcPulseCheck_M	432854207	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	39
T51	3991	1
T53	8762	1
T54	4716	2
T55	8056	1
T58	10447	2
T112	6258	3
T114	5951	2
T118	8586	3
T119	11968	3
T121	12741	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	432854207	39
T51	17417	1
T53	9044	1
T54	4716	2
T55	7733	1
T58	10447	2
T112	42914	3
T114	23804	2
T118	8325	3
T119	11968	3
T121	12741	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T52,T55
1	0	Covered	T50,T52,T55
1	1	Covered	T50,T58,T113

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T52,T55
1	0	Covered	T50,T58,T113
1	1	Covered	T50,T52,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	33	0	0
SrcPulseCheck_M	215619810	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	33
T50	7590	2
T52	14957	1
T55	8056	1
T58	10447	2
T112	6258	3
T113	5825	3
T114	5951	2
T115	14026	2
T116	3300	2
T117	8424	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	215619810	33
T50	3207	2
T52	13598	1
T55	3394	1
T58	4376	2
T112	20643	3
T113	10134	3
T114	11258	2
T115	24131	2
T116	6182	2
T117	7650	3

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T51,T52
1	0	Covered	T50,T51,T52
1	1	Covered	T116

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T51,T52
1	0	Covered	T116
1	1	Covered	T50,T51,T52

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	30	0	0
SrcPulseCheck_M	215619810	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	30
T50	7590	1
T51	3991	1
T52	14957	2
T53	8762	1
T55	8056	1
T58	10447	1
T112	6258	3
T114	5951	2
T115	14026	2
T121	12741	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	215619810	30
T50	3207	1
T51	8164	1
T52	13598	2
T53	3842	1
T55	3394	1
T58	4376	1
T112	20643	3
T114	11258	2
T115	24131	2
T121	5345	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T51,T53
1	0	Covered	T50,T51,T53
1	1	Covered	T54,T112,T121

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T51,T53
1	0	Covered	T54,T112,T121
1	1	Covered	T50,T51,T53

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	31	0	0
SrcPulseCheck_M	107809269	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	31
T50	7590	1
T51	3991	1
T53	8762	1
T54	4716	3
T56	12980	1
T58	10447	1
T112	6258	2
T115	14026	1
T119	11968	2
T121	12741	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	107809269	31
T50	1604	1
T51	4081	1
T53	1920	1
T54	1044	3
T56	2952	1
T58	2189	1
T112	10321	2
T115	12065	1
T119	2400	2
T121	2674	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T54,T56
1	0	Covered	T51,T54,T56
1	1	Covered	T54,T113,T121

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T54,T56
1	0	Covered	T54,T113,T121
1	1	Covered	T51,T54,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	26	0	0
SrcPulseCheck_M	107809269	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	26
T51	3991	1
T54	4716	3
T56	12980	1
T58	10447	1
T112	6258	1
T113	5825	2
T116	3300	1
T121	12741	2
T122	7967	1
T123	2604	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	107809269	26
T51	4081	1
T54	1044	3
T56	2952	1
T58	2189	1
T112	10321	1
T113	5068	2
T116	3092	1
T121	2674	2
T122	3497	1
T123	5996	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T52,T57
1	0	Covered	T51,T52,T57
1	1	Covered	T52,T58,T112

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T52,T57
1	0	Covered	T52,T58,T112
1	1	Covered	T51,T52,T57

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	42	0	0
SrcPulseCheck_M	461463260	42	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	42
T51	3991	2
T52	14957	2
T53	8762	1
T54	4716	1
T55	8056	1
T57	5558	1
T58	10447	3
T112	6258	3
T119	11968	1
T121	12741	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	461463260	42
T51	18144	2
T52	30524	2
T53	9421	1
T54	4913	1
T55	8056	1
T57	5558	1
T58	10884	3
T112	44704	3
T119	12468	1
T121	13273	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T51,T52
1	0	Covered	T50,T51,T52
1	1	Covered	T57,T58,T123

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T50,T51,T52
1	0	Covered	T57,T58,T123
1	1	Covered	T50,T51,T52

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	44	0	0
SrcPulseCheck_M	461463260	44	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	44
T50	7590	1
T51	3991	2
T52	14957	1
T54	4716	1
T55	8056	1
T57	5558	2
T58	10447	3
T112	6258	3
T119	11968	1
T121	12741	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	461463260	44
T50	7744	1
T51	18144	2
T52	30524	1
T54	4913	1
T55	8056	1
T57	5558	2
T58	10884	3
T112	44704	3
T119	12468	1
T121	13273	2

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T52,T55
1	0	Covered	T51,T52,T55
1	1	Covered	T51,T124

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T52,T55
1	0	Covered	T51,T124
1	1	Covered	T51,T52,T55

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	35	0	0
SrcPulseCheck_M	221638800	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	35
T51	3991	2
T52	14957	1
T54	4716	1
T55	8056	1
T58	10447	1
T113	5825	1
T114	5951	1
T118	8586	1
T121	12741	1
T122	7967	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	221638800	35
T51	8708	2
T52	14651	1
T54	2358	1
T55	3866	1
T58	5224	1
T113	11185	1
T114	11902	1
T118	4163	1
T121	6370	1
T122	7967	3

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T52,T54
1	0	Covered	T51,T52,T54
1	1	Covered	T58,T114,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T51,T52,T54
1	0	Covered	T58,T114,T122
1	1	Covered	T51,T52,T54

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153303526	34	0	0
SrcPulseCheck_M	221638800	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153303526	34
T51	3991	1
T52	14957	1
T54	4716	1
T58	10447	2
T113	5825	3
T114	5951	2
T120	2718	1
T121	12741	1
T122	7967	2
T125	9537	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	221638800	34
T51	8708	1
T52	14651	1
T54	2358	1
T58	5224	2
T113	11185	3
T114	11902	2
T120	10038	1
T121	6370	1
T122	7967	2
T125	4578	2

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	430021190	92910	0	0
SrcPulseCheck_M	16088635	91629	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	430021190	92910
T1	194010	88
T2	237784	114
T3	0	112
T5	24614	24
T11	0	50
T12	0	1055
T13	0	38
T14	0	73
T15	0	239
T18	28701	0
T19	4294	0
T20	6785	0
T21	5123	0
T22	1380	0
T23	27315	0
T35	2027	0
T36	0	57

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16088635	91629
T1	426	88
T2	507	114
T3	0	112
T5	60	24
T11	0	50
T12	0	1055
T13	0	38
T14	0	73
T15	0	239
T18	2093	0
T19	313	0
T20	495	0
T21	373	0
T22	100	0
T23	1991	0
T35	148	0
T36	0	57

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	214249558	92181	0	0
SrcPulseCheck_M	16088635	90902	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	214249558	92181
T1	96986	88
T2	118852	114
T3	0	112
T5	12288	24
T11	0	49
T12	0	1051
T13	0	38
T14	0	73
T15	0	239
T18	10212	0
T19	2121	0
T20	3366	0
T21	2733	0
T22	657	0
T23	16174	0
T35	946	0
T36	0	57

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16088635	90902
T1	426	88
T2	507	114
T3	0	112
T5	60	24
T11	0	49
T12	0	1051
T13	0	38
T14	0	73
T15	0	239
T18	2093	0
T19	313	0
T20	495	0
T21	373	0
T22	100	0
T23	1991	0
T35	148	0
T36	0	57

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	107124136	90814	0	0
SrcPulseCheck_M	16088635	89542	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	107124136	90814
T1	48493	88
T2	59426	114
T3	0	112
T5	6144	24
T11	0	43
T12	0	1029
T13	0	38
T14	0	73
T15	0	239
T18	5111	0
T19	1061	0
T20	1683	0
T21	1367	0
T22	329	0
T23	8086	0
T35	473	0
T36	0	57

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16088635	89542
T1	426	88
T2	507	114
T3	0	112
T5	60	24
T11	0	43
T12	0	1029
T13	0	38
T14	0	73
T15	0	239
T18	2093	0
T19	313	0
T20	495	0
T21	373	0
T22	100	0
T23	1991	0
T35	148	0
T36	0	57

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	458512082	110169	0	0
SrcPulseCheck_M	16331997	110035	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	458512082	110169
T1	202100	85
T2	247699	114
T3	0	112
T5	37641	48
T11	0	43
T12	0	1154
T13	0	38
T14	0	73
T15	0	311
T18	29899	0
T19	4474	0
T20	7068	0
T21	5337	0
T22	1438	0
T23	28454	0
T35	2112	0
T36	0	129

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16331997	110035
T1	426	85
T2	507	114
T3	0	112
T5	84	48
T11	0	43
T12	0	1154
T13	0	38
T14	0	73
T15	0	311
T18	2093	0
T19	313	0
T20	495	0
T21	373	0
T22	100	0
T23	1991	0
T35	148	0
T36	0	129

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	220222263	109018	0	0
SrcPulseCheck_M	16279439	108977	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	220222263	109018
T1	97009	75
T2	118898	114
T3	0	112
T5	18067	48
T11	0	43
T12	0	1070
T13	0	38
T14	0	73
T15	0	323
T18	14351	0
T19	2147	0
T20	3393	0
T21	2562	0
T22	690	0
T23	13658	0
T35	1013	0
T36	0	105

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16279439	108977
T1	426	75
T2	507	114
T3	0	112
T5	84	48
T11	0	43
T12	0	1070
T13	0	38
T14	0	73
T15	0	323
T18	2093	0
T19	313	0
T20	495	0
T21	373	0
T22	100	0
T23	1991	0
T35	148	0
T36	0	105

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb