Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	153303526	4569748	0	0
clk_enables_rd_A	153303526	56991	0	0
clk_hints_rd_A	153303526	50849	0	0
extclk_ctrl_rd_A	153303526	65645	0	0
extclk_ctrl_regwen_rd_A	153303526	50366	0	0
jitter_enable_rd_A	153303526	70714	0	0
jitter_regwen_rd_A	153303526	56145	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153303526	4569748	0	0
T12	263567	78535	0	0
T13	137373	0	0	0
T14	98118	0	0	0
T15	562820	0	0	0
T17	0	128607	0	0
T32	0	48698	0	0
T36	93313	0	0	0
T59	0	31160	0	0
T60	0	113486	0	0
T61	0	28247	0	0
T62	0	18623	0	0
T63	0	75307	0	0
T64	0	103379	0	0
T65	0	81090	0	0
T66	3524	0	0	0
T67	1994	0	0	0
T68	1774	0	0	0
T69	1042	0	0	0
T70	121090	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153303526	56991	0	0
T12	263567	3027	0	0
T13	137373	0	0	0
T14	98118	0	0	0
T15	562820	0	0	0
T17	0	4949	0	0
T32	0	1910	0	0
T36	93313	0	0	0
T59	0	1185	0	0
T61	0	529	0	0
T63	0	3033	0	0
T66	3524	0	0	0
T67	1994	0	0	0
T68	1774	0	0	0
T69	1042	0	0	0
T70	121090	0	0	0
T126	0	7	0	0
T127	0	7	0	0
T128	0	2	0	0
T129	0	1250	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153303526	50849	0	0
T12	263567	2693	0	0
T13	137373	0	0	0
T14	98118	0	0	0
T15	562820	0	0	0
T17	0	4351	0	0
T32	0	1712	0	0
T36	93313	0	0	0
T59	0	1100	0	0
T61	0	487	0	0
T63	0	2650	0	0
T66	3524	0	0	0
T67	1994	0	0	0
T68	1774	0	0	0
T69	1042	0	0	0
T70	121090	0	0	0
T126	0	3	0	0
T127	0	8	0	0
T128	0	7	0	0
T129	0	1092	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153303526	65645	0	0
T4	0	25	0	0
T5	36888	0	0	0
T7	1447	28	0	0
T8	1444	0	0	0
T12	0	3438	0	0
T23	0	81	0	0
T26	1439	0	0	0
T27	1867	18	0	0
T28	946	3	0	0
T29	1054	0	0	0
T30	2107	19	0	0
T31	1720	0	0	0
T34	0	52	0	0
T35	1985	0	0	0
T67	0	29	0	0
T130	0	2	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153303526	50366	0	0
T3	68757	0	0	0
T4	21055	1	0	0
T11	13626	0	0	0
T12	263567	2466	0	0
T17	0	4523	0	0
T32	0	1738	0	0
T34	19709	17	0	0
T45	1709	0	0	0
T48	1704	0	0	0
T59	0	1254	0	0
T61	0	488	0	0
T63	0	2919	0	0
T80	839	0	0	0
T81	1448	0	0	0
T82	1434	0	0	0
T104	0	12	0	0
T131	0	64	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153303526	70714	0	0
T12	263567	4484	0	0
T13	137373	0	0	0
T14	98118	0	0	0
T15	562820	0	0	0
T17	0	5456	0	0
T32	0	2130	0	0
T36	93313	0	0	0
T59	0	1857	0	0
T61	0	454	0	0
T63	0	4065	0	0
T66	3524	0	0	0
T67	1994	0	0	0
T68	1774	0	0	0
T69	1042	0	0	0
T70	121090	0	0	0
T126	0	89	0	0
T127	0	97	0	0
T128	0	99	0	0
T129	0	2139	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153303526	56145	0	0
T12	263567	3151	0	0
T13	137373	0	0	0
T14	98118	0	0	0
T15	562820	0	0	0
T17	0	4728	0	0
T32	0	1900	0	0
T36	93313	0	0	0
T59	0	1221	0	0
T61	0	565	0	0
T63	0	2965	0	0
T66	3524	0	0	0
T67	1994	0	0	0
T68	1774	0	0	0
T69	1042	0	0	0
T70	121090	0	0	0
T129	0	1211	0	0
T132	0	2790	0	0
T133	0	5189	0	0
T134	0	1390	0	0