Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	457137600	403	0	0
StatusRise_A	457137600	403	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457137600	403	0	0
T1	48501	0	0	0
T5	110664	0	0	0
T8	4332	7	0	0
T26	4317	0	0	0
T27	5601	0	0	0
T28	2838	0	0	0
T29	3162	0	0	0
T30	6321	0	0	0
T31	5160	0	0	0
T35	5955	0	0	0
T42	0	7	0	0
T43	0	15	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	12	0	0
T138	0	7	0	0
T139	0	2	0	0
T140	0	10	0	0
T141	0	10	0	0
T142	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457137600	403	0	0
T1	48501	0	0	0
T5	110664	0	0	0
T8	4332	7	0	0
T26	4317	0	0	0
T27	5601	0	0	0
T28	2838	0	0	0
T29	3162	0	0	0
T30	6321	0	0	0
T31	5160	0	0	0
T35	5955	0	0	0
T42	0	7	0	0
T43	0	15	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	12	0	0
T138	0	7	0	0
T139	0	2	0	0
T140	0	10	0	0
T141	0	10	0	0
T142	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152379200	137	0	0
StatusRise_A	152379200	137	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	137	0	0
T1	16167	0	0	0
T5	36888	0	0	0
T8	1444	3	0	0
T26	1439	0	0	0
T27	1867	0	0	0
T28	946	0	0	0
T29	1054	0	0	0
T30	2107	0	0	0
T31	1720	0	0	0
T35	1985	0	0	0
T42	0	3	0	0
T43	0	4	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	137	0	0
T1	16167	0	0	0
T5	36888	0	0	0
T8	1444	3	0	0
T26	1439	0	0	0
T27	1867	0	0	0
T28	946	0	0	0
T29	1054	0	0	0
T30	2107	0	0	0
T31	1720	0	0	0
T35	1985	0	0	0
T42	0	3	0	0
T43	0	4	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152379200	129	0	0
StatusRise_A	152379200	129	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	129	0	0
T1	16167	0	0	0
T5	36888	0	0	0
T8	1444	1	0	0
T26	1439	0	0	0
T27	1867	0	0	0
T28	946	0	0	0
T29	1054	0	0	0
T30	2107	0	0	0
T31	1720	0	0	0
T35	1985	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T140	0	4	0	0
T141	0	4	0	0
T142	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	129	0	0
T1	16167	0	0	0
T5	36888	0	0	0
T8	1444	1	0	0
T26	1439	0	0	0
T27	1867	0	0	0
T28	946	0	0	0
T29	1054	0	0	0
T30	2107	0	0	0
T31	1720	0	0	0
T35	1985	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T140	0	4	0	0
T141	0	4	0	0
T142	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152379200	137	0	0
StatusRise_A	152379200	137	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	137	0	0
T1	16167	0	0	0
T5	36888	0	0	0
T8	1444	3	0	0
T26	1439	0	0	0
T27	1867	0	0	0
T28	946	0	0	0
T29	1054	0	0	0
T30	2107	0	0	0
T31	1720	0	0	0
T35	1985	0	0	0
T42	0	2	0	0
T43	0	7	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152379200	137	0	0
T1	16167	0	0	0
T5	36888	0	0	0
T8	1444	3	0	0
T26	1439	0	0	0
T27	1867	0	0	0
T28	946	0	0	0
T29	1054	0	0	0
T30	2107	0	0	0
T31	1720	0	0	0
T35	1985	0	0	0
T42	0	2	0	0
T43	0	7	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	4	0	0