Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50396	0	0
CgEnOn_A	2147483647	41162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50396	0	0
T1	1746084	0	0	0
T5	360360	3	0	0
T6	5310	30	0	0
T7	35224	3	0	0
T8	15162	14	0	0
T20	0	3	0	0
T26	32272	6	0	0
T27	20210	3	0	0
T28	35300	3	0	0
T29	42238	3	0	0
T30	39444	3	0	0
T31	18512	3	0	0
T35	18077	1	0	0
T42	0	10	0	0
T43	0	20	0	0
T60	0	5	0	0
T62	0	5	0	0
T65	0	5	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	20	0	0
T138	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41162	0	0
T1	1746084	0	0	0
T5	360360	0	0	0
T6	5310	18	0	0
T7	35224	0	0	0
T8	15162	7	0	0
T12	0	222	0	0
T15	0	78	0	0
T19	0	9	0	0
T24	0	29	0	0
T26	32272	0	0	0
T27	20210	0	0	0
T28	35300	0	0	0
T29	42238	0	0	0
T30	39444	0	0	0
T31	18512	0	0	0
T35	18077	2	0	0
T42	0	10	0	0
T43	0	20	0	0
T45	0	2	0	0
T60	0	4	0	0
T62	0	4	0	0
T65	0	4	0	0
T69	0	9	0	0
T80	0	8	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	20	0	0
T138	0	15	0	0
T140	0	4	0	0
T141	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	214249558	142	0	0
CgEnOn_A	214249558	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214249558	142	0	0
T1	96986	0	0	0
T5	12288	0	0	0
T8	657	1	0	0
T26	1413	0	0	0
T27	866	0	0	0
T28	1582	0	0	0
T29	1895	0	0	0
T30	1799	0	0	0
T31	809	0	0	0
T35	946	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214249558	142	0	0
T1	96986	0	0	0
T5	12288	0	0	0
T8	657	1	0	0
T26	1413	0	0	0
T27	866	0	0	0
T28	1582	0	0	0
T29	1895	0	0	0
T30	1799	0	0	0
T31	809	0	0	0
T35	946	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107124136	142	0	0
CgEnOn_A	107124136	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124136	142	0	0
T1	48493	0	0	0
T5	6144	0	0	0
T8	329	1	0	0
T26	706	0	0	0
T27	433	0	0	0
T28	790	0	0	0
T29	948	0	0	0
T30	899	0	0	0
T31	405	0	0	0
T35	473	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124136	142	0	0
T1	48493	0	0	0
T5	6144	0	0	0
T8	329	1	0	0
T26	706	0	0	0
T27	433	0	0	0
T28	790	0	0	0
T29	948	0	0	0
T30	899	0	0	0
T31	405	0	0	0
T35	473	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107124136	142	0	0
CgEnOn_A	107124136	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124136	142	0	0
T1	48493	0	0	0
T5	6144	0	0	0
T8	329	1	0	0
T26	706	0	0	0
T27	433	0	0	0
T28	790	0	0	0
T29	948	0	0	0
T30	899	0	0	0
T31	405	0	0	0
T35	473	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124136	142	0	0
T1	48493	0	0	0
T5	6144	0	0	0
T8	329	1	0	0
T26	706	0	0	0
T27	433	0	0	0
T28	790	0	0	0
T29	948	0	0	0
T30	899	0	0	0
T31	405	0	0	0
T35	473	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107124136	142	0	0
CgEnOn_A	107124136	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124136	142	0	0
T1	48493	0	0	0
T5	6144	0	0	0
T8	329	1	0	0
T26	706	0	0	0
T27	433	0	0	0
T28	790	0	0	0
T29	948	0	0	0
T30	899	0	0	0
T31	405	0	0	0
T35	473	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124136	142	0	0
T1	48493	0	0	0
T5	6144	0	0	0
T8	329	1	0	0
T26	706	0	0	0
T27	433	0	0	0
T28	790	0	0	0
T29	948	0	0	0
T30	899	0	0	0
T31	405	0	0	0
T35	473	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	430021190	142	0	0
CgEnOn_A	430021190	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430021190	142	0	0
T1	194010	0	0	0
T5	24614	0	0	0
T8	1366	1	0	0
T26	2878	0	0	0
T27	1810	0	0	0
T28	3132	0	0	0
T29	3746	0	0	0
T30	3486	0	0	0
T31	1651	0	0	0
T35	2027	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430021190	131	0	0
T1	194010	0	0	0
T5	24614	0	0	0
T8	1366	1	0	0
T26	2878	0	0	0
T27	1810	0	0	0
T28	3132	0	0	0
T29	3746	0	0	0
T30	3486	0	0	0
T31	1651	0	0	0
T35	2027	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T140	0	4	0	0
T141	0	4	0	0
T142	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	458512082	138	0	0
CgEnOn_A	458512082	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	138	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T26	2998	0	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	0	0	0
T42	0	3	0	0
T43	0	4	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	137	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T26	2998	0	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	0	0	0
T42	0	3	0	0
T43	0	4	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	458512082	138	0	0
CgEnOn_A	458512082	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	138	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T26	2998	0	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	0	0	0
T42	0	3	0	0
T43	0	4	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	137	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T26	2998	0	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	0	0	0
T42	0	3	0	0
T43	0	4	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	3	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	220222263	140	0	0
CgEnOn_A	220222263	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220222263	140	0	0
T1	97009	0	0	0
T5	18067	0	0	0
T8	679	3	0	0
T26	1439	0	0	0
T27	905	0	0	0
T28	1567	0	0	0
T29	1873	0	0	0
T30	1743	0	0	0
T31	826	0	0	0
T35	1013	0	0	0
T42	0	2	0	0
T43	0	7	0	0
T61	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220222263	138	0	0
T1	97009	0	0	0
T5	18067	0	0	0
T8	679	3	0	0
T26	1439	0	0	0
T27	905	0	0	0
T28	1567	0	0	0
T29	1873	0	0	0
T30	1743	0	0	0
T31	826	0	0	0
T35	1013	0	0	0
T42	0	2	0	0
T43	0	7	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T42,T43
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107124136	8030	0	0
CgEnOn_A	107124136	5732	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124136	8030	0	0
T5	6144	1	0	0
T6	586	10	0	0
T7	4022	1	0	0
T8	329	2	0	0
T26	706	1	0	0
T27	433	1	0	0
T28	790	1	0	0
T29	948	1	0	0
T30	899	1	0	0
T31	405	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107124136	5732	0	0
T5	6144	0	0	0
T6	586	9	0	0
T7	4022	0	0	0
T8	329	1	0	0
T12	0	109	0	0
T15	0	41	0	0
T19	0	4	0	0
T24	0	15	0	0
T26	706	0	0	0
T27	433	0	0	0
T28	790	0	0	0
T29	948	0	0	0
T30	899	0	0	0
T31	405	0	0	0
T35	0	1	0	0
T45	0	1	0	0
T69	0	5	0	0
T80	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T42,T43
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	214249558	8126	0	0
CgEnOn_A	214249558	5828	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214249558	8126	0	0
T5	12288	1	0	0
T6	1172	10	0	0
T7	8044	1	0	0
T8	657	2	0	0
T26	1413	1	0	0
T27	866	1	0	0
T28	1582	1	0	0
T29	1895	1	0	0
T30	1799	1	0	0
T31	809	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214249558	5828	0	0
T5	12288	0	0	0
T6	1172	9	0	0
T7	8044	0	0	0
T8	657	1	0	0
T12	0	113	0	0
T15	0	37	0	0
T19	0	5	0	0
T24	0	14	0	0
T26	1413	0	0	0
T27	866	0	0	0
T28	1582	0	0	0
T29	1895	0	0	0
T30	1799	0	0	0
T31	809	0	0	0
T35	0	1	0	0
T45	0	1	0	0
T69	0	4	0	0
T80	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T42,T43
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	430021190	8089	0	0
CgEnOn_A	430021190	5780	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430021190	8089	0	0
T5	24614	1	0	0
T6	2368	10	0	0
T7	15438	1	0	0
T8	1366	2	0	0
T26	2878	1	0	0
T27	1810	1	0	0
T28	3132	1	0	0
T29	3746	1	0	0
T30	3486	1	0	0
T31	1651	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430021190	5780	0	0
T5	24614	0	0	0
T6	2368	9	0	0
T7	15438	0	0	0
T8	1366	1	0	0
T12	0	116	0	0
T15	0	38	0	0
T19	0	4	0	0
T24	0	14	0	0
T26	2878	0	0	0
T27	1810	0	0	0
T28	3132	0	0	0
T29	3746	0	0	0
T30	3486	0	0	0
T31	1651	0	0	0
T35	0	1	0	0
T45	0	1	0	0
T69	0	4	0	0
T80	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T42,T43
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	220222263	8101	0	0
CgEnOn_A	220222263	5791	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220222263	8101	0	0
T5	18067	1	0	0
T6	1184	8	0	0
T7	7720	1	0	0
T8	679	4	0	0
T26	1439	1	0	0
T27	905	1	0	0
T28	1567	1	0	0
T29	1873	1	0	0
T30	1743	1	0	0
T31	826	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220222263	5791	0	0
T5	18067	0	0	0
T6	1184	7	0	0
T7	7720	0	0	0
T8	679	3	0	0
T12	0	113	0	0
T15	0	37	0	0
T19	0	5	0	0
T24	0	15	0	0
T26	1439	0	0	0
T27	905	0	0	0
T28	1567	0	0	0
T29	1873	0	0	0
T30	1743	0	0	0
T31	826	0	0	0
T35	0	1	0	0
T45	0	1	0	0
T69	0	4	0	0
T80	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Covered	T26,T35,T20
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	458512082	4220	0	0
CgEnOn_A	458512082	4219	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	4220	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T12	0	84	0	0
T15	0	4	0	0
T20	0	3	0	0
T25	0	1	0	0
T26	2998	3	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	11	0	0
T106	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	4219	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T12	0	84	0	0
T15	0	4	0	0
T20	0	3	0	0
T25	0	1	0	0
T26	2998	3	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	11	0	0
T106	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Covered	T26,T35,T20
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	458512082	4228	0	0
CgEnOn_A	458512082	4227	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	4228	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T12	0	88	0	0
T15	0	5	0	0
T20	0	2	0	0
T26	2998	3	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	13	0	0
T106	0	4	0	0
T107	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	4227	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T12	0	88	0	0
T15	0	5	0	0
T20	0	2	0	0
T26	2998	3	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	13	0	0
T106	0	4	0	0
T107	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Covered	T26,T35,T20
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	458512082	4296	0	0
CgEnOn_A	458512082	4295	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	4296	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T12	0	102	0	0
T15	0	5	0	0
T20	0	7	0	0
T25	0	2	0	0
T26	2998	2	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	5	0	0
T106	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	4295	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T12	0	102	0	0
T15	0	5	0	0
T20	0	7	0	0
T25	0	2	0	0
T26	2998	2	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	5	0	0
T106	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T4
1	0	Covered	T26,T35,T20
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	458512082	4180	0	0
CgEnOn_A	458512082	4179	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	4180	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T12	0	90	0	0
T15	0	3	0	0
T20	0	6	0	0
T25	0	2	0	0
T26	2998	3	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	7	0	0
T106	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458512082	4179	0	0
T1	202100	0	0	0
T5	37641	0	0	0
T8	1407	3	0	0
T12	0	90	0	0
T15	0	3	0	0
T20	0	6	0	0
T25	0	2	0	0
T26	2998	3	0	0
T27	1886	0	0	0
T28	3263	0	0	0
T29	3903	0	0	0
T30	3632	0	0	0
T31	1720	0	0	0
T35	2112	1	0	0
T45	0	1	0	0
T66	0	7	0	0
T106	0	4	0	0