Unified Coverage Report :: Module :: clkmgr_clk_status

Module : clkmgr_clk_status

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_main_status	100.00	100.00				100.00
tb.dut.u_io_status	100.00	100.00				100.00
tb.dut.u_usb_status	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_en_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_en_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_en_sync	100.00	100.00				100.00

Line Coverage for Module : clkmgr_clk_status

	Line No.	Total	Covered	Percent
TOTAL		13	13	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	39	5	5	100.00
ALWAYS	49	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
36	1	1
39	1	1
40	1	1
41	1	1
43	1	1
44	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE

---

Branch Coverage for Module : clkmgr_clk_status

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	39	2	2	100.00
IF	49	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	49	if ((!rst_ni))
-2-:	51	if ((&en_q))
-3-:	53	if ((&dis_q))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T7,T8
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T6,T7,T8

Line Coverage for Instance : tb.dut.u_main_status

	Line No.	Total	Covered	Percent
TOTAL		13	13	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	39	5	5	100.00
ALWAYS	49	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
36	1	1
39	1	1
40	1	1
41	1	1
43	1	1
44	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_main_status

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	39	2	2	100.00
IF	49	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	49	if ((!rst_ni))
-2-:	51	if ((&en_q))
-3-:	53	if ((&dis_q))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T7,T8
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T6,T7,T8

Line Coverage for Instance : tb.dut.u_io_status

	Line No.	Total	Covered	Percent
TOTAL		13	13	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	39	5	5	100.00
ALWAYS	49	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
36	1	1
39	1	1
40	1	1
41	1	1
43	1	1
44	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_io_status

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	39	2	2	100.00
IF	49	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	49	if ((!rst_ni))
-2-:	51	if ((&en_q))
-3-:	53	if ((&dis_q))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T7,T8
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T6,T7,T8

Line Coverage for Instance : tb.dut.u_usb_status

	Line No.	Total	Covered	Percent
TOTAL		13	13	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	39	5	5	100.00
ALWAYS	49	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
36	1	1
39	1	1
40	1	1
41	1	1
43	1	1
44	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_usb_status

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	39	2	2	100.00
IF	49	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	49	if ((!rst_ni))
-2-:	51	if ((&en_q))
-3-:	53	if ((&dis_q))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T7,T8
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T6,T7,T8