Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	670152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3998090

1

T5

2

T6

7

T1

227

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1144349	1			T5	3		T6	4		T1	49
values[0x0]	1620461	1			T5	4		T6	7		T1	183
values[0x1]	1903432	1			T5	3		T6	2		T1	218

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	365508	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4302734

1

T5

3

T6

8

T1

299

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17582	1			T20	1		T3	183		T10	17
valid_sources[0x01]	18308	1			T2	5		T3	205		T11	4
valid_sources[0x02]	18296	1			T3	232		T68	1		T10	30
valid_sources[0x03]	17792	1			T17	1		T2	5		T3	170
valid_sources[0x04]	18428	1			T17	2		T3	187		T10	5
valid_sources[0x05]	18762	1			T20	1		T3	178		T12	615
valid_sources[0x06]	19229	1			T6	2		T17	1		T3	179
valid_sources[0x07]	17349	1			T17	1		T3	212		T66	4
valid_sources[0x08]	17980	1			T4	35		T17	1		T2	4
valid_sources[0x09]	17548	1			T20	1		T3	195		T10	34
valid_sources[0x0a]	18339	1			T3	175		T9	5		T10	18
valid_sources[0x0b]	18750	1			T2	2		T3	216		T9	3
valid_sources[0x0c]	18592	1			T17	1		T2	1		T3	169
valid_sources[0x0d]	20225	1			T3	188		T9	4		T12	435
valid_sources[0x0e]	17737	1			T3	182		T9	2		T12	644
valid_sources[0x0f]	18241	1			T6	2		T4	1		T2	5
valid_sources[0x10]	17962	1			T17	1		T3	206		T11	2
valid_sources[0x11]	18105	1			T4	29		T3	176		T64	3
valid_sources[0x12]	20314	1			T20	1		T3	186		T10	30
valid_sources[0x13]	17394	1			T17	2		T20	1		T3	196
valid_sources[0x14]	17516	1			T4	4		T2	6		T3	200
valid_sources[0x15]	17275	1			T3	202		T10	3		T12	379
valid_sources[0x16]	17064	1			T17	1		T2	3		T3	217
valid_sources[0x17]	19645	1			T4	23		T3	192		T81	7
valid_sources[0x18]	19902	1			T17	1		T3	214		T10	21
valid_sources[0x19]	17722	1			T2	5		T3	199		T10	21
valid_sources[0x1a]	18114	1			T5	1		T3	179		T66	9
valid_sources[0x1b]	19444	1			T2	5		T3	195		T10	6
valid_sources[0x1c]	18053	1			T3	195		T10	12		T12	575
valid_sources[0x1d]	19460	1			T2	4		T3	204		T12	925
valid_sources[0x1e]	18745	1			T4	11		T2	3		T3	201
valid_sources[0x1f]	17956	1			T3	192		T10	19		T12	616
valid_sources[0x20]	18576	1			T3	219		T10	16		T12	649
valid_sources[0x21]	17170	1			T4	10		T3	191		T9	10
valid_sources[0x22]	19274	1			T3	168		T66	3		T10	8
valid_sources[0x23]	19054	1			T17	1		T3	193		T12	332
valid_sources[0x24]	18514	1			T2	13		T3	179		T81	4
valid_sources[0x25]	17848	1			T2	1		T3	194		T10	5
valid_sources[0x26]	16986	1			T17	2		T2	8		T3	181
valid_sources[0x27]	17576	1			T17	1		T20	1		T3	188
valid_sources[0x28]	19352	1			T2	2		T3	175		T10	8
valid_sources[0x29]	17683	1			T17	2		T2	5		T3	208
valid_sources[0x2a]	19189	1			T2	5		T3	189		T9	21
valid_sources[0x2b]	17933	1			T2	4		T31	3		T3	184
valid_sources[0x2c]	18339	1			T17	1		T3	179		T9	13
valid_sources[0x2d]	17694	1			T3	173		T10	26		T12	963
valid_sources[0x2e]	19504	1			T3	206		T10	18		T12	1044
valid_sources[0x2f]	17580	1			T2	2		T3	210		T66	3
valid_sources[0x30]	17960	1			T17	1		T2	1		T20	1
valid_sources[0x31]	18678	1			T4	1		T17	1		T3	174
valid_sources[0x32]	18065	1			T17	2		T3	202		T63	3
valid_sources[0x33]	17961	1			T2	3		T3	213		T81	1
valid_sources[0x34]	20527	1			T17	1		T2	1		T3	183
valid_sources[0x35]	18136	1			T17	2		T3	210		T10	1
valid_sources[0x36]	18848	1			T17	1		T3	209		T9	5
valid_sources[0x37]	18732	1			T4	3		T17	1		T20	1
valid_sources[0x38]	17817	1			T17	1		T2	12		T3	196
valid_sources[0x39]	17604	1			T17	1		T2	4		T20	1
valid_sources[0x3a]	16607	1			T3	208		T12	334		T13	386
valid_sources[0x3b]	18857	1			T3	163		T12	471		T13	411
valid_sources[0x3c]	19721	1			T2	1		T3	197		T10	1
valid_sources[0x3d]	18215	1			T5	1		T17	2		T3	185
valid_sources[0x3e]	18604	1			T3	170		T12	929		T13	366
valid_sources[0x3f]	20726	1			T17	1		T31	2		T3	188
valid_sources[0x40]	20180	1			T17	2		T3	218		T9	5
valid_sources[0x41]	16886	1			T2	1		T3	187		T10	5
valid_sources[0x42]	19255	1			T17	1		T20	1		T3	174
valid_sources[0x43]	17752	1			T3	220		T10	4		T12	429
valid_sources[0x44]	18522	1			T17	2		T3	183		T10	4
valid_sources[0x45]	17864	1			T17	1		T20	1		T31	3
valid_sources[0x46]	17351	1			T3	192		T9	7		T12	727
valid_sources[0x47]	17462	1			T5	3		T2	1		T3	191
valid_sources[0x48]	16941	1			T2	15		T3	187		T9	13
valid_sources[0x49]	19747	1			T6	1		T17	4		T3	188
valid_sources[0x4a]	18902	1			T3	205		T10	21		T12	1303
valid_sources[0x4b]	17942	1			T3	152		T10	13		T12	480
valid_sources[0x4c]	18107	1			T17	1		T2	2		T3	189
valid_sources[0x4d]	18079	1			T2	4		T3	184		T9	10
valid_sources[0x4e]	18553	1			T4	2		T3	189		T10	11
valid_sources[0x4f]	17909	1			T2	1		T3	175		T9	4
valid_sources[0x50]	16957	1			T2	1		T18	1		T3	160
valid_sources[0x51]	17505	1			T3	218		T66	2		T11	6
valid_sources[0x52]	16932	1			T5	2		T3	187		T66	6
valid_sources[0x53]	17431	1			T3	198		T11	7		T12	285
valid_sources[0x54]	17989	1			T3	196		T10	34		T12	779
valid_sources[0x55]	18633	1			T3	190		T10	5		T12	759
valid_sources[0x56]	18386	1			T17	3		T3	216		T9	17
valid_sources[0x57]	16975	1			T6	1		T3	206		T10	2
valid_sources[0x58]	16639	1			T3	172		T10	3		T11	2
valid_sources[0x59]	18167	1			T2	12		T3	202		T12	463
valid_sources[0x5a]	19244	1			T17	4		T3	183		T10	14
valid_sources[0x5b]	19939	1			T3	187		T9	21		T10	8
valid_sources[0x5c]	18153	1			T17	1		T2	1		T3	204
valid_sources[0x5d]	17944	1			T4	11		T2	15		T3	188
valid_sources[0x5e]	19001	1			T3	177		T10	14		T81	2
valid_sources[0x5f]	18758	1			T3	203		T10	27		T109	91
valid_sources[0x60]	17147	1			T17	2		T2	24		T3	179
valid_sources[0x61]	17737	1			T2	3		T3	177		T10	24
valid_sources[0x62]	18555	1			T3	215		T10	20		T81	1
valid_sources[0x63]	18413	1			T3	178		T12	1030		T13	380
valid_sources[0x64]	17485	1			T2	3		T3	183		T9	1
valid_sources[0x65]	16952	1			T2	1		T3	187		T9	4
valid_sources[0x66]	17966	1			T17	1		T2	1		T20	1
valid_sources[0x67]	17571	1			T4	13		T2	2		T3	198
valid_sources[0x68]	18030	1			T2	2		T3	178		T9	12
valid_sources[0x69]	18412	1			T4	14		T17	1		T3	202
valid_sources[0x6a]	18113	1			T4	5		T17	3		T3	149
valid_sources[0x6b]	17103	1			T2	3		T3	186		T10	24
valid_sources[0x6c]	17822	1			T3	195		T10	23		T12	298
valid_sources[0x6d]	18011	1			T17	2		T2	4		T3	218
valid_sources[0x6e]	19378	1			T3	188		T10	5		T12	992
valid_sources[0x6f]	19483	1			T2	2		T3	173		T11	2
valid_sources[0x70]	17761	1			T3	153		T10	26		T12	514
valid_sources[0x71]	18330	1			T17	1		T3	210		T9	9
valid_sources[0x72]	19328	1			T2	3		T3	194		T10	7
valid_sources[0x73]	18382	1			T4	3		T20	1		T3	189
valid_sources[0x74]	18756	1			T2	1		T3	151		T10	18
valid_sources[0x75]	18743	1			T2	5		T3	184		T81	5
valid_sources[0x76]	17734	1			T2	3		T3	225		T63	2
valid_sources[0x77]	17635	1			T17	1		T3	178		T12	441
valid_sources[0x78]	17906	1			T3	165		T10	7		T12	520
valid_sources[0x79]	18930	1			T3	199		T9	9		T10	26
valid_sources[0x7a]	18930	1			T4	4		T17	3		T3	190
valid_sources[0x7b]	19409	1			T17	1		T2	1		T3	216
valid_sources[0x7c]	19038	1			T2	2		T3	212		T10	3
valid_sources[0x7d]	18148	1			T17	1		T2	9		T3	201
valid_sources[0x7e]	19569	1			T3	147		T12	998		T84	1
valid_sources[0x7f]	16597	1			T3	177		T66	1		T10	7
valid_sources[0x80]	18064	1			T17	2		T3	181		T9	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1007525

1

T5

1

T6

2

T1

29

values[0x0]

all_enables

biggest_size

1520267

1

T5

1

T6

5

T1

112

values[0x1]

all_enables

biggest_size

1470298

1

T1

86

T4

24

T16

3