Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T19
0	1	Covered	T3,T9,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T3
1	0	Covered	T7,T29,T30
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1090104993	15210	0	0
GateOpen_A	1090104993	21819	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090104993	15210	0	0
T1	483884	0	0	0
T2	457997	0	0	0
T3	0	124	0	0
T4	82131	0	0	0
T7	3012	15	0	0
T9	0	81	0	0
T10	0	73	0	0
T12	0	299	0	0
T13	0	234	0	0
T16	6607	0	0	0
T17	30180	0	0	0
T18	7026	0	0	0
T19	142911	0	0	0
T20	12877	0	0	0
T21	3369	0	0	0
T29	0	18	0	0
T30	0	11	0	0
T32	0	4	0	0
T65	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1090104993	21819	0	0
T1	483884	0	0	0
T2	457997	0	0	0
T4	82131	24	0	0
T5	8369	4	0	0
T6	3921	4	0	0
T7	3012	19	0	0
T16	6607	0	0	0
T17	30180	4	0	0
T18	7026	4	0	0
T19	142911	52	0	0
T20	0	4	0	0
T22	0	4	0	0
T31	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T19
0	1	Covered	T3,T9,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T3
1	0	Covered	T7,T29,T30
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	120220433	3584	0	0
GateOpen_A	120220433	5234	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220433	3584	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T3	0	28	0	0
T4	6552	0	0	0
T7	312	4	0	0
T9	0	19	0	0
T10	0	18	0	0
T12	0	64	0	0
T13	0	58	0	0
T16	721	0	0	0
T17	3336	0	0	0
T18	765	0	0	0
T19	10589	0	0	0
T20	1420	0	0	0
T21	371	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T32	0	1	0	0
T65	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220433	5234	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T4	6552	6	0	0
T5	930	1	0	0
T6	444	1	0	0
T7	312	5	0	0
T16	721	0	0	0
T17	3336	1	0	0
T18	765	1	0	0
T19	10589	13	0	0
T20	0	1	0	0
T22	0	1	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T19
0	1	Covered	T3,T9,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T3
1	0	Covered	T7,T29,T30
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	240441661	3867	0	0
GateOpen_A	240441661	5517	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441661	3867	0	0
T1	107484	0	0	0
T2	101750	0	0	0
T3	0	33	0	0
T4	13103	0	0	0
T7	623	4	0	0
T9	0	19	0	0
T10	0	19	0	0
T12	0	80	0	0
T13	0	58	0	0
T16	1442	0	0	0
T17	6671	0	0	0
T18	1530	0	0	0
T19	21178	0	0	0
T20	2840	0	0	0
T21	741	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T32	0	1	0	0
T65	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441661	5517	0	0
T1	107484	0	0	0
T2	101750	0	0	0
T4	13103	6	0	0
T5	1859	1	0	0
T6	890	1	0	0
T7	623	5	0	0
T16	1442	0	0	0
T17	6671	1	0	0
T18	1530	1	0	0
T19	21178	13	0	0
T20	0	1	0	0
T22	0	1	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T19
0	1	Covered	T3,T9,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T3
1	0	Covered	T7,T29,T30
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	482496951	3873	0	0
GateOpen_A	482496951	5527	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496951	3873	0	0
T1	215102	0	0	0
T2	203578	0	0	0
T3	0	32	0	0
T4	41650	0	0	0
T7	1380	4	0	0
T9	0	20	0	0
T10	0	14	0	0
T12	0	73	0	0
T13	0	57	0	0
T16	2963	0	0	0
T17	13448	0	0	0
T18	3154	0	0	0
T19	74095	0	0	0
T20	5744	0	0	0
T21	1504	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T32	0	1	0	0
T65	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496951	5527	0	0
T1	215102	0	0	0
T2	203578	0	0	0
T4	41650	6	0	0
T5	3720	1	0	0
T6	1725	1	0	0
T7	1380	5	0	0
T16	2963	0	0	0
T17	13448	1	0	0
T18	3154	1	0	0
T19	74095	13	0	0
T20	0	1	0	0
T22	0	1	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T19
0	1	Covered	T3,T9,T10
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T3
1	0	Covered	T7,T29,T30
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	246945948	3886	0	0
GateOpen_A	246945948	5541	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246945948	3886	0	0
T1	107556	0	0	0
T2	101794	0	0	0
T3	0	31	0	0
T4	20826	0	0	0
T7	697	3	0	0
T9	0	23	0	0
T10	0	22	0	0
T12	0	82	0	0
T13	0	61	0	0
T16	1481	0	0	0
T17	6725	0	0	0
T18	1577	0	0	0
T19	37049	0	0	0
T20	2873	0	0	0
T21	753	0	0	0
T29	0	6	0	0
T30	0	2	0	0
T32	0	1	0	0
T65	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246945948	5541	0	0
T1	107556	0	0	0
T2	101794	0	0	0
T4	20826	6	0	0
T5	1860	1	0	0
T6	862	1	0	0
T7	697	4	0	0
T16	1481	0	0	0
T17	6725	1	0	0
T18	1577	1	0	0
T19	37049	13	0	0
T20	0	1	0	0
T22	0	1	0	0
T31	0	1	0	0