Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	855825375	81984	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855825375	81984	0	0
T1	1075505	400	0	0
T2	1060330	528	0	0
T3	0	328	0	0
T4	208245	0	0	0
T9	0	314	0	0
T10	0	1528	0	0
T11	0	115	0	0
T12	0	2137	0	0
T13	0	288	0	0
T14	0	102	0	0
T15	0	315	0	0
T16	6790	0	0	0
T17	17505	0	0	0
T18	3935	0	0	0
T19	192955	0	0	0
T20	7175	0	0	0
T21	7835	0	0	0
T22	11680	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171165075	12032	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	12032	0	0
T1	215101	59	0	0
T2	212066	67	0	0
T3	0	52	0	0
T4	41649	0	0	0
T9	0	40	0	0
T10	0	197	0	0
T11	0	15	0	0
T12	0	317	0	0
T13	0	35	0	0
T14	0	16	0	0
T15	0	47	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T22	2336	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171165075	11906	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	11906	0	0
T1	215101	50	0	0
T2	212066	75	0	0
T3	0	52	0	0
T4	41649	0	0	0
T9	0	45	0	0
T10	0	222	0	0
T11	0	16	0	0
T12	0	268	0	0
T13	0	41	0	0
T14	0	16	0	0
T15	0	39	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T22	2336	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171165075	16550	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	16550	0	0
T1	215101	80	0	0
T2	212066	106	0	0
T3	0	65	0	0
T4	41649	0	0	0
T9	0	64	0	0
T10	0	304	0	0
T11	0	22	0	0
T12	0	424	0	0
T13	0	59	0	0
T14	0	22	0	0
T15	0	62	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T22	2336	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171165075	16517	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	16517	0	0
T1	215101	79	0	0
T2	212066	105	0	0
T3	0	67	0	0
T4	41649	0	0	0
T9	0	63	0	0
T10	0	308	0	0
T11	0	23	0	0
T12	0	434	0	0
T13	0	60	0	0
T14	0	20	0	0
T15	0	64	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T22	2336	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171165075	24979	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	24979	0	0
T1	215101	132	0	0
T2	212066	175	0	0
T3	0	92	0	0
T4	41649	0	0	0
T9	0	102	0	0
T10	0	497	0	0
T11	0	39	0	0
T12	0	694	0	0
T13	0	93	0	0
T14	0	28	0	0
T15	0	103	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T22	2336	0	0	0