Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T19,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	171165075	168421466	0	0
AllClkBypReqTrue_A	171165075	123581	0	0
IoClkBypReqFalse_A	171165075	168335608	0	2415
IoClkBypReqTrue_A	171165075	204777	0	0
LcClkBypAckFalse_A	171165075	168425385	0	0
LcClkBypAckTrue_A	171165075	119662	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	168421466	0	0
T1	215101	214869	0	0
T2	212066	211868	0	0
T4	41649	2579	0	0
T5	929	892	0	0
T6	1779	1507	0	0
T7	1535	1293	0	0
T16	1358	1295	0	0
T17	3501	3451	0	0
T18	787	746	0	0
T19	38591	4999	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	123581	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T3	0	43	0	0
T4	41649	0	0	0
T5	929	13	0	0
T6	1779	47	0	0
T7	1535	0	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T21	0	4	0	0
T31	0	344	0	0
T62	0	240	0	0
T67	0	138	0	0
T70	0	113	0	0
T81	0	360	0	0
T108	0	272	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	168335608	0	2415
T1	215101	214867	0	3
T2	212066	211866	0	3
T4	41649	2565	0	3
T5	929	903	0	3
T6	1779	1347	0	3
T7	1535	1291	0	3
T16	1358	1293	0	3
T17	3501	3449	0	3
T18	787	744	0	3
T19	38591	4973	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	204777	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T3	0	127	0	0
T4	41649	0	0	0
T6	1779	205	0	0
T7	1535	0	0	0
T12	0	6295	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	0	58	0	0
T31	0	424	0	0
T62	0	48	0	0
T70	0	154	0	0
T81	0	447	0	0
T82	0	79	0	0
T108	0	319	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	168425385	0	0
T1	215101	214869	0	0
T2	212066	211868	0	0
T4	41649	2579	0	0
T5	929	905	0	0
T6	1779	1393	0	0
T7	1535	1293	0	0
T16	1358	1295	0	0
T17	3501	3451	0	0
T18	787	746	0	0
T19	38591	4999	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	119662	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T3	0	38	0	0
T4	41649	0	0	0
T6	1779	161	0	0
T7	1535	0	0	0
T12	0	3969	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	0	25	0	0
T31	0	349	0	0
T62	0	44	0	0
T70	0	124	0	0
T81	0	318	0	0
T82	0	40	0	0
T108	0	132	0	0