Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2059214924	16993	0	0
TransStop_A	2059214924	8565	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2059214924	16993	0	0
T2	848268	0	0	0
T3	0	161	0	0
T9	0	48	0	0
T10	0	87	0	0
T17	56040	46	0	0
T18	13140	0	0	0
T19	308736	0	0	0
T20	23940	0	0	0
T21	6272	0	0	0
T22	19460	32	0	0
T31	19684	0	0	0
T32	0	4	0	0
T64	0	18	0	0
T65	0	4	0	0
T66	0	14	0	0
T69	6664	0	0	0
T70	7632	0	0	0
T109	0	23	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2059214924	8565	0	0
T2	848268	0	0	0
T3	0	86	0	0
T9	0	21	0	0
T10	0	40	0	0
T12	0	35	0	0
T17	56040	21	0	0
T18	13140	0	0	0
T19	308736	0	0	0
T20	23940	0	0	0
T21	6272	0	0	0
T22	19460	17	0	0
T31	19684	0	0	0
T32	0	4	0	0
T64	0	15	0	0
T65	0	4	0	0
T66	0	6	0	0
T69	6664	0	0	0
T70	7632	0	0	0
T109	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	514803731	4187	0	0
TransStop_A	514803731	2091	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803731	4187	0	0
T2	212067	0	0	0
T3	0	40	0	0
T9	0	11	0	0
T10	0	24	0	0
T17	14010	10	0	0
T18	3285	0	0	0
T19	77184	0	0	0
T20	5985	0	0	0
T21	1568	0	0	0
T22	4865	8	0	0
T31	4921	0	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	6	0	0
T69	1666	0	0	0
T70	1908	0	0	0
T109	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803731	2091	0	0
T2	212067	0	0	0
T3	0	23	0	0
T9	0	6	0	0
T10	0	11	0	0
T17	14010	4	0	0
T18	3285	0	0	0
T19	77184	0	0	0
T20	5985	0	0	0
T21	1568	0	0	0
T22	4865	4	0	0
T31	4921	0	0	0
T32	0	1	0	0
T64	0	3	0	0
T65	0	1	0	0
T66	0	2	0	0
T69	1666	0	0	0
T70	1908	0	0	0
T109	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	514803731	4236	0	0
TransStop_A	514803731	2157	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803731	4236	0	0
T2	212067	0	0	0
T3	0	34	0	0
T9	0	13	0	0
T10	0	23	0	0
T17	14010	11	0	0
T18	3285	0	0	0
T19	77184	0	0	0
T20	5985	0	0	0
T21	1568	0	0	0
T22	4865	5	0	0
T31	4921	0	0	0
T32	0	1	0	0
T64	0	5	0	0
T65	0	1	0	0
T66	0	4	0	0
T69	1666	0	0	0
T70	1908	0	0	0
T109	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803731	2157	0	0
T2	212067	0	0	0
T3	0	21	0	0
T9	0	5	0	0
T10	0	11	0	0
T17	14010	6	0	0
T18	3285	0	0	0
T19	77184	0	0	0
T20	5985	0	0	0
T21	1568	0	0	0
T22	4865	1	0	0
T31	4921	0	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	3	0	0
T69	1666	0	0	0
T70	1908	0	0	0
T109	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	514803731	4244	0	0
TransStop_A	514803731	2151	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803731	4244	0	0
T2	212067	0	0	0
T3	0	40	0	0
T9	0	14	0	0
T10	0	16	0	0
T17	14010	10	0	0
T18	3285	0	0	0
T19	77184	0	0	0
T20	5985	0	0	0
T21	1568	0	0	0
T22	4865	10	0	0
T31	4921	0	0	0
T32	0	1	0	0
T64	0	5	0	0
T65	0	1	0	0
T66	0	3	0	0
T69	1666	0	0	0
T70	1908	0	0	0
T109	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803731	2151	0	0
T2	212067	0	0	0
T3	0	20	0	0
T9	0	6	0	0
T10	0	7	0	0
T17	14010	5	0	0
T18	3285	0	0	0
T19	77184	0	0	0
T20	5985	0	0	0
T21	1568	0	0	0
T22	4865	5	0	0
T31	4921	0	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	1	0	0
T69	1666	0	0	0
T70	1908	0	0	0
T109	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	514803731	4326	0	0
TransStop_A	514803731	2166	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803731	4326	0	0
T2	212067	0	0	0
T3	0	47	0	0
T9	0	10	0	0
T10	0	24	0	0
T17	14010	15	0	0
T18	3285	0	0	0
T19	77184	0	0	0
T20	5985	0	0	0
T21	1568	0	0	0
T22	4865	9	0	0
T31	4921	0	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	1	0	0
T69	1666	0	0	0
T70	1908	0	0	0
T109	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803731	2166	0	0
T2	212067	0	0	0
T3	0	22	0	0
T9	0	4	0	0
T10	0	11	0	0
T12	0	35	0	0
T17	14010	6	0	0
T18	3285	0	0	0
T19	77184	0	0	0
T20	5985	0	0	0
T21	1568	0	0	0
T22	4865	7	0	0
T31	4921	0	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T69	1666	0	0	0
T70	1908	0	0	0
T109	0	3	0	0