Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	171165075	23747939	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	23747939	0	58
T1	215101	47066	0	1
T2	212066	61087	0	1
T3	0	64830	0	0
T4	41649	0	0	0
T9	0	36876	0	0
T10	0	182023	0	0
T11	0	13052	0	1
T12	0	236744	0	0
T13	0	27978	0	0
T14	0	7004	0	1
T15	0	35666	0	1
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T22	2336	0	0	0
T26	0	0	0	1
T110	0	0	0	1
T111	0	0	0	1
T112	0	0	0	1
T113	0	0	0	1