Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	172081157	5881881	0	0
clk_enables_rd_A	172081157	43907	0	0
clk_hints_rd_A	172081157	38919	0	0
extclk_ctrl_rd_A	172081157	47319	0	0
extclk_ctrl_regwen_rd_A	172081157	36702	0	0
jitter_enable_rd_A	172081157	55607	0	0
jitter_regwen_rd_A	172081157	41806	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172081157	5881881	0	0
T3	133215	64344	0	0
T9	139274	0	0	0
T12	0	229907	0	0
T13	0	132489	0	0
T32	1221	0	0	0
T55	0	95138	0	0
T56	0	86346	0	0
T57	0	6017	0	0
T58	0	54734	0	0
T59	0	155358	0	0
T60	0	61473	0	0
T61	0	167616	0	0
T62	1772	0	0	0
T63	1579	0	0	0
T64	1533	0	0	0
T65	1614	0	0	0
T66	1170	0	0	0
T67	1415	0	0	0
T68	928	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172081157	43907	0	0
T9	139274	7	0	0
T10	119423	1	0	0
T27	0	13	0	0
T32	1221	0	0	0
T55	0	3504	0	0
T60	0	2552	0	0
T62	1772	0	0	0
T63	1579	0	0	0
T64	1533	0	0	0
T65	1614	4	0	0
T66	1170	0	0	0
T67	1415	0	0	0
T68	928	0	0	0
T135	0	6045	0	0
T136	0	4	0	0
T137	0	7	0	0
T138	0	4526	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172081157	38919	0	0
T9	139274	7	0	0
T10	119423	4	0	0
T27	0	8	0	0
T32	1221	0	0	0
T55	0	2896	0	0
T60	0	2461	0	0
T62	1772	0	0	0
T63	1579	0	0	0
T64	1533	0	0	0
T65	1614	10	0	0
T66	1170	0	0	0
T67	1415	0	0	0
T68	928	0	0	0
T135	0	5571	0	0
T136	0	11	0	0
T137	0	2	0	0
T139	0	7	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172081157	47319	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T4	41649	0	0	0
T6	1779	12	0	0
T7	1535	0	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T27	0	41	0	0
T31	0	42	0	0
T55	0	3817	0	0
T62	0	50	0	0
T73	0	65	0	0
T107	0	45	0	0
T140	0	35	0	0
T141	0	14	0	0
T142	0	69	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172081157	36702	0	0
T8	63288	0	0	0
T55	317124	3330	0	0
T56	244115	0	0	0
T60	0	2023	0	0
T71	50929	0	0	0
T87	1796	0	0	0
T107	0	35	0	0
T135	0	5121	0	0
T138	0	3812	0	0
T140	2785	0	0	0
T143	0	38	0	0
T144	0	17	0	0
T145	0	29	0	0
T146	0	40	0	0
T147	0	8	0	0
T148	1583	0	0	0
T149	13031	0	0	0
T150	3962	0	0	0
T151	117348	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172081157	55607	0	0
T9	139274	121	0	0
T10	119423	84	0	0
T27	0	231	0	0
T32	1221	0	0	0
T55	0	4550	0	0
T60	0	3163	0	0
T62	1772	0	0	0
T63	1579	0	0	0
T64	1533	0	0	0
T65	1614	130	0	0
T66	1170	0	0	0
T67	1415	0	0	0
T68	928	0	0	0
T135	0	6622	0	0
T136	0	361	0	0
T137	0	119	0	0
T139	0	132	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172081157	41806	0	0
T8	63288	0	0	0
T55	317124	3632	0	0
T56	244115	0	0	0
T60	0	2296	0	0
T71	50929	0	0	0
T87	1796	0	0	0
T135	0	5711	0	0
T138	0	4397	0	0
T140	2785	0	0	0
T148	1583	0	0	0
T149	13031	0	0	0
T150	3962	0	0	0
T151	117348	0	0	0
T152	0	3876	0	0
T153	0	5228	0	0
T154	0	4692	0	0
T155	0	1727	0	0
T156	0	2145	0	0
T157	0	1034	0	0