Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T31,T3,T62
1	1	Covered	T5,T6,T21

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	482496951	4386	0	0
g_div2.Div2Whole_A	482496951	5266	0	0
g_div4.Div4Stepped_A	240441661	4293	0	0
g_div4.Div4Whole_A	240441661	4933	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496951	4386	0	0
T1	215102	0	0	0
T2	203578	0	0	0
T3	0	1	0	0
T4	41650	0	0	0
T5	3720	1	0	0
T6	1725	3	0	0
T7	1380	0	0	0
T16	2963	0	0	0
T17	13448	0	0	0
T18	3154	0	0	0
T19	74095	0	0	0
T21	0	2	0	0
T31	0	9	0	0
T62	0	9	0	0
T67	0	9	0	0
T70	0	5	0	0
T81	0	11	0	0
T108	0	5	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496951	5266	0	0
T1	215102	0	0	0
T2	203578	0	0	0
T3	0	1	0	0
T4	41650	0	0	0
T5	3720	1	0	0
T6	1725	4	0	0
T7	1380	0	0	0
T16	2963	0	0	0
T17	13448	0	0	0
T18	3154	0	0	0
T19	74095	0	0	0
T21	0	3	0	0
T31	0	9	0	0
T62	0	9	0	0
T67	0	10	0	0
T70	0	7	0	0
T81	0	11	0	0
T108	0	6	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441661	4293	0	0
T1	107484	0	0	0
T2	101750	0	0	0
T3	0	1	0	0
T4	13103	0	0	0
T5	1859	1	0	0
T6	890	3	0	0
T7	623	0	0	0
T16	1442	0	0	0
T17	6671	0	0	0
T18	1530	0	0	0
T19	21178	0	0	0
T21	0	2	0	0
T31	0	9	0	0
T62	0	9	0	0
T67	0	9	0	0
T70	0	4	0	0
T81	0	11	0	0
T108	0	5	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441661	4933	0	0
T1	107484	0	0	0
T2	101750	0	0	0
T3	0	1	0	0
T4	13103	0	0	0
T5	1859	1	0	0
T6	890	4	0	0
T7	623	0	0	0
T16	1442	0	0	0
T17	6671	0	0	0
T18	1530	0	0	0
T19	21178	0	0	0
T21	0	3	0	0
T31	0	9	0	0
T62	0	9	0	0
T67	0	10	0	0
T70	0	3	0	0
T81	0	11	0	0
T108	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T31,T3,T62
1	1	Covered	T5,T6,T21

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	482496951	4386	0	0
g_div2.Div2Whole_A	482496951	5266	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496951	4386	0	0
T1	215102	0	0	0
T2	203578	0	0	0
T3	0	1	0	0
T4	41650	0	0	0
T5	3720	1	0	0
T6	1725	3	0	0
T7	1380	0	0	0
T16	2963	0	0	0
T17	13448	0	0	0
T18	3154	0	0	0
T19	74095	0	0	0
T21	0	2	0	0
T31	0	9	0	0
T62	0	9	0	0
T67	0	9	0	0
T70	0	5	0	0
T81	0	11	0	0
T108	0	5	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496951	5266	0	0
T1	215102	0	0	0
T2	203578	0	0	0
T3	0	1	0	0
T4	41650	0	0	0
T5	3720	1	0	0
T6	1725	4	0	0
T7	1380	0	0	0
T16	2963	0	0	0
T17	13448	0	0	0
T18	3154	0	0	0
T19	74095	0	0	0
T21	0	3	0	0
T31	0	9	0	0
T62	0	9	0	0
T67	0	10	0	0
T70	0	7	0	0
T81	0	11	0	0
T108	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T31,T3,T62
1	1	Covered	T5,T6,T21

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	240441661	4293	0	0
g_div4.Div4Whole_A	240441661	4933	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441661	4293	0	0
T1	107484	0	0	0
T2	101750	0	0	0
T3	0	1	0	0
T4	13103	0	0	0
T5	1859	1	0	0
T6	890	3	0	0
T7	623	0	0	0
T16	1442	0	0	0
T17	6671	0	0	0
T18	1530	0	0	0
T19	21178	0	0	0
T21	0	2	0	0
T31	0	9	0	0
T62	0	9	0	0
T67	0	9	0	0
T70	0	4	0	0
T81	0	11	0	0
T108	0	5	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441661	4933	0	0
T1	107484	0	0	0
T2	101750	0	0	0
T3	0	1	0	0
T4	13103	0	0	0
T5	1859	1	0	0
T6	890	4	0	0
T7	623	0	0	0
T16	1442	0	0	0
T17	6671	0	0	0
T18	1530	0	0	0
T19	21178	0	0	0
T21	0	3	0	0
T31	0	9	0	0
T62	0	9	0	0
T67	0	10	0	0
T70	0	3	0	0
T81	0	11	0	0
T108	0	6	0	0