Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	513495225	404	0	0
StatusRise_A	513495225	404	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513495225	404	0	0
T1	645303	0	0	0
T2	636198	0	0	0
T4	124947	0	0	0
T7	4605	10	0	0
T16	4074	0	0	0
T17	10503	0	0	0
T18	2361	0	0	0
T19	115773	0	0	0
T20	4305	0	0	0
T21	4701	0	0	0
T29	0	14	0	0
T30	0	8	0	0
T42	0	1	0	0
T158	0	3	0	0
T159	0	16	0	0
T160	0	9	0	0
T161	0	2	0	0
T162	0	5	0	0
T163	0	11	0	0
T164	0	6	0	0
T165	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513495225	404	0	0
T1	645303	0	0	0
T2	636198	0	0	0
T4	124947	0	0	0
T7	4605	10	0	0
T16	4074	0	0	0
T17	10503	0	0	0
T18	2361	0	0	0
T19	115773	0	0	0
T20	4305	0	0	0
T21	4701	0	0	0
T29	0	14	0	0
T30	0	8	0	0
T42	0	1	0	0
T158	0	3	0	0
T159	0	16	0	0
T160	0	9	0	0
T161	0	2	0	0
T162	0	5	0	0
T163	0	11	0	0
T164	0	6	0	0
T165	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	171165075	135	0	0
StatusRise_A	171165075	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	135	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T4	41649	0	0	0
T7	1535	3	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T42	0	1	0	0
T158	0	1	0	0
T159	0	6	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	135	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T4	41649	0	0	0
T7	1535	3	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T42	0	1	0	0
T158	0	1	0	0
T159	0	6	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	171165075	142	0	0
StatusRise_A	171165075	142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	142	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T4	41649	0	0	0
T7	1535	4	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0
T164	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	142	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T4	41649	0	0	0
T7	1535	4	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0
T164	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	171165075	127	0	0
StatusRise_A	171165075	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	127	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T4	41649	0	0	0
T7	1535	3	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T29	0	6	0	0
T30	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171165075	127	0	0
T1	215101	0	0	0
T2	212066	0	0	0
T4	41649	0	0	0
T7	1535	3	0	0
T16	1358	0	0	0
T17	3501	0	0	0
T18	787	0	0	0
T19	38591	0	0	0
T20	1435	0	0	0
T21	1567	0	0	0
T29	0	6	0	0
T30	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	1	0	0