Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	52119	0	0
CgEnOn_A	2147483647	42791	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52119	0	0
T1	2419672	3	0	0
T2	2290136	3	0	0
T3	0	40	0	0
T4	437680	21	0	0
T5	8365	3	0	0
T6	3920	3	0	0
T7	15176	38	0	0
T16	33168	3	0	0
T17	151082	13	0	0
T18	35282	3	0	0
T19	770102	39	0	0
T20	51619	0	0	0
T21	13509	0	0	0
T22	0	8	0	0
T29	0	20	0	0
T30	0	15	0	0
T55	0	10	0	0
T158	0	5	0	0
T159	0	25	0	0
T160	0	15	0	0
T161	0	5	0	0
T162	0	5	0	0
T163	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42791	0	0
T1	2419672	0	0	0
T2	2290136	0	0	0
T3	0	199	0	0
T4	437680	0	0	0
T7	15176	35	0	0
T9	0	108	0	0
T10	0	94	0	0
T12	0	362	0	0
T13	0	286	0	0
T16	33168	0	0	0
T17	151082	10	0	0
T18	35282	0	0	0
T19	770102	0	0	0
T20	64494	0	0	0
T21	16876	0	0	0
T22	0	8	0	0
T29	0	32	0	0
T30	0	24	0	0
T32	0	4	0	0
T55	0	8	0	0
T64	0	4	0	0
T65	0	4	0	0
T158	0	5	0	0
T159	0	25	0	0
T160	0	15	0	0
T161	0	5	0	0
T162	0	5	0	0
T163	0	15	0	0
T164	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240441259	149	0	0
CgEnOn_A	240441259	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441259	149	0	0
T1	107483	0	0	0
T2	101749	0	0	0
T4	13103	0	0	0
T7	623	4	0	0
T16	1441	0	0	0
T17	6671	0	0	0
T18	1530	0	0	0
T19	21178	0	0	0
T20	2839	0	0	0
T21	741	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441259	149	0	0
T1	107483	0	0	0
T2	101749	0	0	0
T4	13103	0	0	0
T7	623	4	0	0
T16	1441	0	0	0
T17	6671	0	0	0
T18	1530	0	0	0
T19	21178	0	0	0
T20	2839	0	0	0
T21	741	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120220038	149	0	0
CgEnOn_A	120220038	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220038	149	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T4	6551	0	0	0
T7	311	4	0	0
T16	721	0	0	0
T17	3335	0	0	0
T18	765	0	0	0
T19	10589	0	0	0
T20	1420	0	0	0
T21	370	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220038	149	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T4	6551	0	0	0
T7	311	4	0	0
T16	721	0	0	0
T17	3335	0	0	0
T18	765	0	0	0
T19	10589	0	0	0
T20	1420	0	0	0
T21	370	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120220038	149	0	0
CgEnOn_A	120220038	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220038	149	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T4	6551	0	0	0
T7	311	4	0	0
T16	721	0	0	0
T17	3335	0	0	0
T18	765	0	0	0
T19	10589	0	0	0
T20	1420	0	0	0
T21	370	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220038	149	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T4	6551	0	0	0
T7	311	4	0	0
T16	721	0	0	0
T17	3335	0	0	0
T18	765	0	0	0
T19	10589	0	0	0
T20	1420	0	0	0
T21	370	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120220038	149	0	0
CgEnOn_A	120220038	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220038	149	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T4	6551	0	0	0
T7	311	4	0	0
T16	721	0	0	0
T17	3335	0	0	0
T18	765	0	0	0
T19	10589	0	0	0
T20	1420	0	0	0
T21	370	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220038	149	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T4	6551	0	0	0
T7	311	4	0	0
T16	721	0	0	0
T17	3335	0	0	0
T18	765	0	0	0
T19	10589	0	0	0
T20	1420	0	0	0
T21	370	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	482496515	149	0	0
CgEnOn_A	482496515	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496515	149	0	0
T1	215101	0	0	0
T2	203578	0	0	0
T4	41649	0	0	0
T7	1380	4	0	0
T16	2962	0	0	0
T17	13448	0	0	0
T18	3153	0	0	0
T19	74094	0	0	0
T20	5744	0	0	0
T21	1504	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T55	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496515	144	0	0
T1	215101	0	0	0
T2	203578	0	0	0
T4	41649	0	0	0
T7	1380	4	0	0
T16	2962	0	0	0
T17	13448	0	0	0
T18	3153	0	0	0
T19	74094	0	0	0
T20	5744	0	0	0
T21	1504	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0
T164	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	514803257	137	0	0
CgEnOn_A	514803257	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	137	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T16	3086	0	0	0
T17	14009	0	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T42	0	1	0	0
T158	0	1	0	0
T159	0	6	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	135	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T16	3086	0	0	0
T17	14009	0	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T42	0	1	0	0
T158	0	1	0	0
T159	0	6	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	514803257	137	0	0
CgEnOn_A	514803257	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	137	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T16	3086	0	0	0
T17	14009	0	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T42	0	1	0	0
T158	0	1	0	0
T159	0	6	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	135	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T16	3086	0	0	0
T17	14009	0	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T42	0	1	0	0
T158	0	1	0	0
T159	0	6	0	0
T160	0	3	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	246945586	130	0	0
CgEnOn_A	246945586	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246945586	130	0	0
T1	107555	0	0	0
T2	101793	0	0	0
T4	20825	0	0	0
T7	697	3	0	0
T16	1481	0	0	0
T17	6725	0	0	0
T18	1576	0	0	0
T19	37049	0	0	0
T20	2872	0	0	0
T21	752	0	0	0
T29	0	6	0	0
T30	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246945586	127	0	0
T1	107555	0	0	0
T2	101793	0	0	0
T4	20825	0	0	0
T7	697	3	0	0
T16	1481	0	0	0
T17	6725	0	0	0
T18	1576	0	0	0
T19	37049	0	0	0
T20	2872	0	0	0
T21	752	0	0	0
T29	0	6	0	0
T30	0	2	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	3	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T29,T30
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120220038	8286	0	0
CgEnOn_A	120220038	5962	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220038	8286	0	0
T1	53742	1	0	0
T2	50875	1	0	0
T4	6551	7	0	0
T5	929	1	0	0
T6	444	1	0	0
T7	311	5	0	0
T16	721	1	0	0
T17	3335	1	0	0
T18	765	1	0	0
T19	10589	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120220038	5962	0	0
T1	53742	0	0	0
T2	50875	0	0	0
T3	0	50	0	0
T4	6551	0	0	0
T7	311	4	0	0
T9	0	34	0	0
T10	0	24	0	0
T12	0	115	0	0
T13	0	95	0	0
T16	721	0	0	0
T17	3335	0	0	0
T18	765	0	0	0
T19	10589	0	0	0
T20	1420	0	0	0
T21	370	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T32	0	1	0	0
T65	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T29,T30
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240441259	8357	0	0
CgEnOn_A	240441259	6033	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441259	8357	0	0
T1	107483	1	0	0
T2	101749	1	0	0
T4	13103	7	0	0
T5	1858	1	0	0
T6	889	1	0	0
T7	623	5	0	0
T16	1441	1	0	0
T17	6671	1	0	0
T18	1530	1	0	0
T19	21178	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240441259	6033	0	0
T1	107483	0	0	0
T2	101749	0	0	0
T3	0	55	0	0
T4	13103	0	0	0
T7	623	4	0	0
T9	0	29	0	0
T10	0	25	0	0
T12	0	130	0	0
T13	0	94	0	0
T16	1441	0	0	0
T17	6671	0	0	0
T18	1530	0	0	0
T19	21178	0	0	0
T20	2839	0	0	0
T21	741	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T32	0	1	0	0
T65	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T29,T30
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	482496515	8413	0	0
CgEnOn_A	482496515	6084	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496515	8413	0	0
T1	215101	1	0	0
T2	203578	1	0	0
T4	41649	7	0	0
T5	3719	1	0	0
T6	1725	1	0	0
T7	1380	5	0	0
T16	2962	1	0	0
T17	13448	1	0	0
T18	3153	1	0	0
T19	74094	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482496515	6084	0	0
T1	215101	0	0	0
T2	203578	0	0	0
T3	0	54	0	0
T4	41649	0	0	0
T7	1380	4	0	0
T9	0	34	0	0
T10	0	21	0	0
T12	0	117	0	0
T13	0	97	0	0
T16	2962	0	0	0
T17	13448	0	0	0
T18	3153	0	0	0
T19	74094	0	0	0
T20	5744	0	0	0
T21	1504	0	0	0
T29	0	4	0	0
T30	0	3	0	0
T32	0	1	0	0
T65	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T29,T30
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	246945586	8373	0	0
CgEnOn_A	246945586	6042	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246945586	8373	0	0
T1	107555	1	0	0
T2	101793	1	0	0
T4	20825	7	0	0
T5	1859	1	0	0
T6	862	1	0	0
T7	697	4	0	0
T16	1481	1	0	0
T17	6725	1	0	0
T18	1576	1	0	0
T19	37049	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246945586	6042	0	0
T1	107555	0	0	0
T2	101793	0	0	0
T3	0	55	0	0
T4	20825	0	0	0
T7	697	3	0	0
T9	0	35	0	0
T10	0	27	0	0
T12	0	129	0	0
T13	0	92	0	0
T16	1481	0	0	0
T17	6725	0	0	0
T18	1576	0	0	0
T19	37049	0	0	0
T20	2872	0	0	0
T21	752	0	0	0
T29	0	6	0	0
T30	0	2	0	0
T32	0	1	0	0
T65	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Covered	T17,T22,T3
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	514803257	4324	0	0
CgEnOn_A	514803257	4322	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	4324	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T3	0	40	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T9	0	11	0	0
T10	0	24	0	0
T16	3086	0	0	0
T17	14009	10	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T22	0	8	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	4322	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T3	0	40	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T9	0	11	0	0
T10	0	24	0	0
T16	3086	0	0	0
T17	14009	10	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T22	0	8	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Covered	T17,T22,T3
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	514803257	4373	0	0
CgEnOn_A	514803257	4371	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	4373	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T3	0	34	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T9	0	13	0	0
T10	0	23	0	0
T16	3086	0	0	0
T17	14009	11	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T22	0	5	0	0
T32	0	1	0	0
T64	0	5	0	0
T65	0	1	0	0
T66	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	4371	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T3	0	34	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T9	0	13	0	0
T10	0	23	0	0
T16	3086	0	0	0
T17	14009	11	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T22	0	5	0	0
T32	0	1	0	0
T64	0	5	0	0
T65	0	1	0	0
T66	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Covered	T17,T22,T3
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	514803257	4381	0	0
CgEnOn_A	514803257	4379	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	4381	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T3	0	40	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T9	0	14	0	0
T10	0	16	0	0
T16	3086	0	0	0
T17	14009	10	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T22	0	10	0	0
T32	0	1	0	0
T64	0	5	0	0
T65	0	1	0	0
T66	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	4379	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T3	0	40	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T9	0	14	0	0
T10	0	16	0	0
T16	3086	0	0	0
T17	14009	10	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T22	0	10	0	0
T32	0	1	0	0
T64	0	5	0	0
T65	0	1	0	0
T66	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T19
1	0	Covered	T17,T22,T3
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	514803257	4463	0	0
CgEnOn_A	514803257	4461	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	4463	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T3	0	47	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T9	0	10	0	0
T10	0	24	0	0
T16	3086	0	0	0
T17	14009	15	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T22	0	9	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514803257	4461	0	0
T1	224071	0	0	0
T2	212066	0	0	0
T3	0	47	0	0
T4	43387	0	0	0
T7	1422	3	0	0
T9	0	10	0	0
T10	0	24	0	0
T16	3086	0	0	0
T17	14009	15	0	0
T18	3284	0	0	0
T19	77184	0	0	0
T20	5984	0	0	0
T21	1567	0	0	0
T22	0	9	0	0
T32	0	1	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	1	0	0