Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	613824	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3590643

1

T5

223

T7

8

T25

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1036302	1			T5	63		T7	9		T25	20
values[0x0]	1456703	1			T5	213		T7	11		T25	15
values[0x1]	1711462	1			T5	205		T7	8		T25	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	336901	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3867566

1

T5

282

T7

10

T25

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16663	1			T2	846		T3	459		T31	3
valid_sources[0x01]	18709	1			T5	4		T22	1		T24	1
valid_sources[0x02]	14894	1			T25	1		T2	759		T3	486
valid_sources[0x03]	16642	1			T2	842		T3	464		T80	5
valid_sources[0x04]	15937	1			T19	81		T2	827		T3	423
valid_sources[0x05]	15087	1			T2	749		T3	461		T31	4
valid_sources[0x06]	16458	1			T24	1		T2	904		T3	488
valid_sources[0x07]	16423	1			T46	1		T2	894		T3	425
valid_sources[0x08]	16444	1			T24	3		T2	788		T3	432
valid_sources[0x09]	16087	1			T2	855		T3	428		T161	1
valid_sources[0x0a]	15267	1			T22	1		T2	684		T28	1
valid_sources[0x0b]	15853	1			T5	2		T46	11		T2	817
valid_sources[0x0c]	15281	1			T17	1		T21	3		T2	772
valid_sources[0x0d]	16947	1			T46	4		T2	662		T3	442
valid_sources[0x0e]	16476	1			T5	9		T46	7		T2	795
valid_sources[0x0f]	17621	1			T25	1		T24	1		T2	711
valid_sources[0x10]	16017	1			T25	1		T2	822		T3	462
valid_sources[0x11]	15406	1			T7	1		T2	806		T3	495
valid_sources[0x12]	17044	1			T5	2		T21	1		T2	765
valid_sources[0x13]	17577	1			T24	3		T2	759		T3	436
valid_sources[0x14]	15944	1			T5	4		T22	1		T2	733
valid_sources[0x15]	15442	1			T2	710		T3	406		T112	2
valid_sources[0x16]	16635	1			T2	719		T3	409		T35	1
valid_sources[0x17]	16413	1			T18	3		T24	1		T2	803
valid_sources[0x18]	16040	1			T2	947		T3	457		T32	1
valid_sources[0x19]	17039	1			T5	1		T46	13		T2	785
valid_sources[0x1a]	17640	1			T2	716		T3	468		T31	5
valid_sources[0x1b]	16280	1			T18	5		T2	820		T3	427
valid_sources[0x1c]	16246	1			T18	1		T2	724		T3	434
valid_sources[0x1d]	16629	1			T24	1		T2	759		T3	471
valid_sources[0x1e]	15993	1			T5	1		T25	1		T2	810
valid_sources[0x1f]	15681	1			T1	434		T17	4		T22	3
valid_sources[0x20]	16826	1			T5	11		T7	1		T25	1
valid_sources[0x21]	16663	1			T5	4		T2	826		T28	1
valid_sources[0x22]	15843	1			T2	675		T3	439		T31	1
valid_sources[0x23]	15877	1			T25	2		T46	9		T2	827
valid_sources[0x24]	16676	1			T2	697		T3	465		T162	2
valid_sources[0x25]	16012	1			T2	718		T3	445		T31	3
valid_sources[0x26]	15832	1			T5	11		T2	700		T3	432
valid_sources[0x27]	16208	1			T7	1		T25	1		T2	784
valid_sources[0x28]	15650	1			T2	816		T3	381		T31	1
valid_sources[0x29]	17729	1			T7	2		T25	1		T2	741
valid_sources[0x2a]	17477	1			T5	7		T2	790		T3	439
valid_sources[0x2b]	16852	1			T17	1		T24	2		T2	689
valid_sources[0x2c]	17229	1			T2	659		T3	465		T155	2
valid_sources[0x2d]	17049	1			T5	3		T2	721		T3	435
valid_sources[0x2e]	16514	1			T5	1		T2	849		T28	1
valid_sources[0x2f]	16109	1			T24	2		T2	774		T3	431
valid_sources[0x30]	16473	1			T5	2		T2	746		T3	474
valid_sources[0x31]	15916	1			T2	731		T3	398		T163	1
valid_sources[0x32]	16253	1			T5	3		T2	879		T3	437
valid_sources[0x33]	15325	1			T46	2		T2	777		T3	428
valid_sources[0x34]	15114	1			T5	4		T7	1		T2	843
valid_sources[0x35]	15451	1			T5	5		T2	753		T3	426
valid_sources[0x36]	15799	1			T2	859		T3	422		T164	4
valid_sources[0x37]	16586	1			T5	2		T2	794		T3	425
valid_sources[0x38]	16692	1			T2	809		T3	454		T35	2
valid_sources[0x39]	17436	1			T5	1		T2	831		T3	427
valid_sources[0x3a]	16340	1			T2	794		T3	416		T31	3
valid_sources[0x3b]	15711	1			T2	721		T3	473		T112	3
valid_sources[0x3c]	17315	1			T5	9		T2	846		T3	444
valid_sources[0x3d]	17461	1			T5	2		T2	734		T3	454
valid_sources[0x3e]	18007	1			T46	8		T2	857		T3	464
valid_sources[0x3f]	16288	1			T5	9		T2	778		T3	433
valid_sources[0x40]	14971	1			T24	1		T46	10		T2	809
valid_sources[0x41]	17563	1			T5	5		T25	1		T2	823
valid_sources[0x42]	15639	1			T24	1		T2	607		T3	438
valid_sources[0x43]	15834	1			T21	1		T22	2		T2	758
valid_sources[0x44]	16935	1			T5	3		T2	819		T3	486
valid_sources[0x45]	15838	1			T2	899		T3	466		T163	1
valid_sources[0x46]	17391	1			T17	2		T2	792		T3	447
valid_sources[0x47]	15577	1			T2	737		T3	403		T108	52
valid_sources[0x48]	15163	1			T2	638		T3	443		T159	10
valid_sources[0x49]	17927	1			T5	2		T21	2		T2	781
valid_sources[0x4a]	16052	1			T5	11		T7	1		T24	1
valid_sources[0x4b]	17514	1			T2	767		T3	395		T32	1
valid_sources[0x4c]	17799	1			T5	1		T25	1		T24	1
valid_sources[0x4d]	15861	1			T24	2		T46	13		T2	781
valid_sources[0x4e]	16532	1			T2	840		T3	408		T32	1
valid_sources[0x4f]	17491	1			T25	1		T2	851		T3	442
valid_sources[0x50]	16267	1			T5	1		T24	1		T2	779
valid_sources[0x51]	17357	1			T2	725		T3	374		T165	1
valid_sources[0x52]	16643	1			T46	3		T2	604		T3	472
valid_sources[0x53]	16411	1			T2	808		T3	431		T38	1
valid_sources[0x54]	16179	1			T5	1		T7	2		T2	679
valid_sources[0x55]	16615	1			T2	764		T3	428		T31	1
valid_sources[0x56]	16469	1			T2	739		T3	453		T31	1
valid_sources[0x57]	16566	1			T24	1		T2	761		T28	1
valid_sources[0x58]	15669	1			T2	852		T3	430		T31	5
valid_sources[0x59]	17777	1			T22	1		T2	791		T28	1
valid_sources[0x5a]	15334	1			T24	1		T2	609		T3	472
valid_sources[0x5b]	15135	1			T46	1		T2	746		T3	403
valid_sources[0x5c]	17032	1			T7	1		T24	1		T46	2
valid_sources[0x5d]	17530	1			T5	10		T2	773		T3	439
valid_sources[0x5e]	17375	1			T2	717		T3	437		T31	2
valid_sources[0x5f]	16641	1			T46	4		T2	699		T3	419
valid_sources[0x60]	16198	1			T5	7		T7	1		T2	715
valid_sources[0x61]	17848	1			T46	17		T2	786		T3	453
valid_sources[0x62]	17004	1			T17	7		T2	866		T3	436
valid_sources[0x63]	16369	1			T24	1		T2	781		T3	482
valid_sources[0x64]	15676	1			T5	2		T25	1		T18	1
valid_sources[0x65]	16263	1			T5	5		T7	1		T24	2
valid_sources[0x66]	15664	1			T24	1		T2	737		T3	438
valid_sources[0x67]	16172	1			T5	3		T21	1		T2	770
valid_sources[0x68]	16084	1			T7	1		T25	1		T2	751
valid_sources[0x69]	15574	1			T24	3		T2	739		T28	2
valid_sources[0x6a]	17380	1			T5	3		T24	1		T46	11
valid_sources[0x6b]	16911	1			T2	794		T3	433		T35	4
valid_sources[0x6c]	15328	1			T46	6		T2	758		T3	418
valid_sources[0x6d]	15811	1			T46	5		T2	897		T3	446
valid_sources[0x6e]	16573	1			T5	5		T2	793		T3	423
valid_sources[0x6f]	16288	1			T21	1		T2	864		T3	414
valid_sources[0x70]	16123	1			T5	7		T2	801		T3	442
valid_sources[0x71]	15252	1			T2	800		T3	427		T10	6
valid_sources[0x72]	15775	1			T5	13		T2	812		T3	425
valid_sources[0x73]	17408	1			T25	1		T21	1		T2	779
valid_sources[0x74]	17410	1			T21	1		T2	876		T3	457
valid_sources[0x75]	15173	1			T5	5		T2	770		T3	413
valid_sources[0x76]	16801	1			T7	1		T17	8		T2	736
valid_sources[0x77]	15836	1			T5	11		T22	2		T2	836
valid_sources[0x78]	17735	1			T5	5		T46	8		T2	733
valid_sources[0x79]	17133	1			T5	3		T23	111		T2	772
valid_sources[0x7a]	16100	1			T24	1		T2	809		T28	1
valid_sources[0x7b]	15348	1			T2	917		T3	427		T165	1
valid_sources[0x7c]	15051	1			T5	2		T18	1		T2	828
valid_sources[0x7d]	17788	1			T5	12		T25	1		T46	2
valid_sources[0x7e]	17019	1			T22	2		T24	1		T2	749
valid_sources[0x7f]	15693	1			T5	5		T7	1		T2	708
valid_sources[0x80]	16157	1			T2	759		T3	470		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

908428

1

T5

27

T7

3

T25

9

values[0x0]

all_enables

biggest_size

1364362

1

T5

130

T7

4

T25

6

values[0x1]

all_enables

biggest_size

1317853

1

T5

66

T7

1

T25

5