Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T19
0	1	Covered	T5,T46,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T4
1	0	Covered	T6,T20,T45
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	938536892	12888	0	0
GateOpen_A	938536892	19428	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938536892	12888	0	0
T1	457484	0	0	0
T2	0	135	0	0
T3	0	331	0	0
T4	258213	0	0	0
T5	384265	30	0	0
T6	4146	13	0	0
T7	7613	0	0	0
T17	14047	0	0	0
T18	11584	0	0	0
T19	7571	3	0	0
T20	15525	12	0	0
T25	5435	0	0	0
T45	0	18	0	0
T46	0	8	0	0
T112	0	4	0	0
T143	0	12	0	0
T144	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938536892	19428	0	0
T1	457484	4	0	0
T4	258213	64	0	0
T5	384265	42	0	0
T6	4146	17	0	0
T7	7613	4	0	0
T17	14047	4	0	0
T18	11584	4	0	0
T19	7571	7	0	0
T20	15525	16	0	0
T21	0	4	0	0
T25	5435	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T46,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T46
1	0	Covered	T6,T20,T45
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	103467887	3055	0	0
GateOpen_A	103467887	4689	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467887	3055	0	0
T1	50809	0	0	0
T2	0	28	0	0
T3	0	83	0	0
T4	21486	0	0	0
T5	39203	8	0	0
T6	438	3	0	0
T7	885	0	0	0
T17	1548	0	0	0
T18	1270	0	0	0
T19	835	0	0	0
T20	1724	3	0	0
T25	610	0	0	0
T45	0	5	0	0
T46	0	2	0	0
T112	0	1	0	0
T143	0	3	0	0
T144	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103467887	4689	0	0
T1	50809	1	0	0
T4	21486	16	0	0
T5	39203	11	0	0
T6	438	4	0	0
T7	885	1	0	0
T17	1548	1	0	0
T18	1270	1	0	0
T19	835	1	0	0
T20	1724	4	0	0
T21	0	1	0	0
T25	610	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T19
0	1	Covered	T5,T46,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T4
1	0	Covered	T6,T20,T45
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	206936636	3265	0	0
GateOpen_A	206936636	4899	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206936636	3265	0	0
T1	101618	0	0	0
T2	0	32	0	0
T3	0	87	0	0
T4	42975	0	0	0
T5	78407	7	0	0
T6	876	3	0	0
T7	1772	0	0	0
T17	3095	0	0	0
T18	2539	0	0	0
T19	1670	1	0	0
T20	3447	3	0	0
T25	1222	0	0	0
T45	0	5	0	0
T46	0	2	0	0
T112	0	1	0	0
T143	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206936636	4899	0	0
T1	101618	1	0	0
T4	42975	16	0	0
T5	78407	10	0	0
T6	876	4	0	0
T7	1772	1	0	0
T17	3095	1	0	0
T18	2539	1	0	0
T19	1670	2	0	0
T20	3447	4	0	0
T21	0	1	0	0
T25	1222	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T19
0	1	Covered	T5,T46,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T4
1	0	Covered	T6,T20,T45
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	415562283	3287	0	0
GateOpen_A	415562283	4923	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415562283	3287	0	0
T1	203368	0	0	0
T2	0	36	0	0
T3	0	81	0	0
T4	129166	0	0	0
T5	156647	7	0	0
T6	1887	3	0	0
T7	3304	0	0	0
T17	6269	0	0	0
T18	5183	0	0	0
T19	3378	1	0	0
T20	6946	3	0	0
T25	2402	0	0	0
T45	0	5	0	0
T46	0	2	0	0
T112	0	1	0	0
T143	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415562283	4923	0	0
T1	203368	1	0	0
T4	129166	16	0	0
T5	156647	10	0	0
T6	1887	4	0	0
T7	3304	1	0	0
T17	6269	1	0	0
T18	5183	1	0	0
T19	3378	2	0	0
T20	6946	4	0	0
T21	0	1	0	0
T25	2402	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T19
0	1	Covered	T5,T46,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T4
1	0	Covered	T6,T20,T45
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	212570086	3281	0	0
GateOpen_A	212570086	4917	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212570086	3281	0	0
T1	101689	0	0	0
T2	0	39	0	0
T3	0	80	0	0
T4	64586	0	0	0
T5	110008	8	0	0
T6	945	4	0	0
T7	1652	0	0	0
T17	3135	0	0	0
T18	2592	0	0	0
T19	1688	1	0	0
T20	3408	3	0	0
T25	1201	0	0	0
T45	0	3	0	0
T46	0	2	0	0
T112	0	1	0	0
T143	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212570086	4917	0	0
T1	101689	1	0	0
T4	64586	16	0	0
T5	110008	11	0	0
T6	945	5	0	0
T7	1652	1	0	0
T17	3135	1	0	0
T18	2592	1	0	0
T19	1688	2	0	0
T20	3408	4	0	0
T21	0	1	0	0
T25	1201	0	0	0