Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	818514320	78820	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818514320	78820	0	0
T1	1027495	472	0	0
T2	0	1975	0	0
T3	0	2881	0	0
T4	134550	0	0	0
T10	0	95	0	0
T11	0	318	0	0
T12	0	2919	0	0
T13	0	228	0	0
T14	0	1789	0	0
T15	0	277	0	0
T16	0	2022	0	0
T17	7830	0	0	0
T18	6745	0	0	0
T19	7560	0	0	0
T20	5085	0	0	0
T21	5285	0	0	0
T22	8435	0	0	0
T23	153485	0	0	0
T24	8810	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163702864	11502	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	11502	0	0
T1	205499	61	0	0
T2	0	266	0	0
T3	0	407	0	0
T4	26910	0	0	0
T10	0	15	0	0
T11	0	47	0	0
T12	0	378	0	0
T13	0	37	0	0
T14	0	235	0	0
T15	0	44	0	0
T16	0	297	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T21	1057	0	0	0
T22	1687	0	0	0
T23	30697	0	0	0
T24	1762	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163702864	11341	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	11341	0	0
T1	205499	60	0	0
T2	0	254	0	0
T3	0	408	0	0
T4	26910	0	0	0
T10	0	15	0	0
T11	0	40	0	0
T12	0	372	0	0
T13	0	34	0	0
T14	0	230	0	0
T15	0	44	0	0
T16	0	253	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T21	1057	0	0	0
T22	1687	0	0	0
T23	30697	0	0	0
T24	1762	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163702864	16024	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	16024	0	0
T1	205499	97	0	0
T2	0	398	0	0
T3	0	579	0	0
T4	26910	0	0	0
T10	0	20	0	0
T11	0	63	0	0
T12	0	593	0	0
T13	0	47	0	0
T14	0	360	0	0
T15	0	56	0	0
T16	0	400	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T21	1057	0	0	0
T22	1687	0	0	0
T23	30697	0	0	0
T24	1762	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163702864	15825	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	15825	0	0
T1	205499	96	0	0
T2	0	401	0	0
T3	0	585	0	0
T4	26910	0	0	0
T10	0	19	0	0
T11	0	65	0	0
T12	0	595	0	0
T13	0	47	0	0
T14	0	362	0	0
T15	0	56	0	0
T16	0	406	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T21	1057	0	0	0
T22	1687	0	0	0
T23	30697	0	0	0
T24	1762	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163702864	24128	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	24128	0	0
T1	205499	158	0	0
T2	0	656	0	0
T3	0	902	0	0
T4	26910	0	0	0
T10	0	26	0	0
T11	0	103	0	0
T12	0	981	0	0
T13	0	63	0	0
T14	0	602	0	0
T15	0	77	0	0
T16	0	666	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T21	1057	0	0	0
T22	1687	0	0	0
T23	30697	0	0	0
T24	1762	0	0	0