Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
T25 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5444478 |
5437766 |
0 |
0 |
T4 |
1975093 |
799521 |
0 |
0 |
T5 |
3130312 |
3125102 |
0 |
0 |
T6 |
36842 |
33809 |
0 |
0 |
T7 |
65974 |
63340 |
0 |
0 |
T17 |
101008 |
98554 |
0 |
0 |
T18 |
84242 |
81867 |
0 |
0 |
T19 |
63776 |
62430 |
0 |
0 |
T20 |
101616 |
99669 |
0 |
0 |
T25 |
64333 |
62712 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
982217184 |
965942400 |
0 |
14490 |
T1 |
1232994 |
1231332 |
0 |
18 |
T4 |
161460 |
52386 |
0 |
18 |
T5 |
225768 |
225318 |
0 |
18 |
T6 |
6324 |
5802 |
0 |
18 |
T7 |
10320 |
9840 |
0 |
18 |
T17 |
9396 |
9120 |
0 |
18 |
T18 |
8094 |
7824 |
0 |
18 |
T19 |
9072 |
8838 |
0 |
18 |
T20 |
6102 |
5952 |
0 |
18 |
T25 |
14562 |
14142 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
1461762 |
1459790 |
0 |
21 |
T4 |
721197 |
235008 |
0 |
21 |
T5 |
1148619 |
1146377 |
0 |
21 |
T6 |
11130 |
10102 |
0 |
21 |
T7 |
20512 |
19569 |
0 |
21 |
T17 |
35521 |
34502 |
0 |
21 |
T18 |
29477 |
28534 |
0 |
21 |
T19 |
20473 |
19968 |
0 |
21 |
T20 |
37828 |
36929 |
0 |
21 |
T25 |
17264 |
16766 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
192471 |
0 |
0 |
T1 |
1461762 |
4 |
0 |
0 |
T2 |
0 |
713 |
0 |
0 |
T3 |
0 |
1099 |
0 |
0 |
T4 |
721197 |
68 |
0 |
0 |
T5 |
1148619 |
151 |
0 |
0 |
T6 |
11130 |
21 |
0 |
0 |
T7 |
20512 |
115 |
0 |
0 |
T17 |
35521 |
12 |
0 |
0 |
T18 |
29477 |
63 |
0 |
0 |
T19 |
20473 |
12 |
0 |
0 |
T20 |
37828 |
40 |
0 |
0 |
T21 |
0 |
26 |
0 |
0 |
T22 |
0 |
92 |
0 |
0 |
T25 |
17264 |
176 |
0 |
0 |
T29 |
0 |
61 |
0 |
0 |
T30 |
0 |
81 |
0 |
0 |
T32 |
0 |
14 |
0 |
0 |
T46 |
0 |
32 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2749722 |
2746605 |
0 |
0 |
T4 |
1092436 |
511336 |
0 |
0 |
T5 |
1755925 |
1753290 |
0 |
0 |
T6 |
19388 |
17866 |
0 |
0 |
T7 |
35142 |
33892 |
0 |
0 |
T17 |
56091 |
54893 |
0 |
0 |
T18 |
46671 |
45470 |
0 |
0 |
T19 |
34231 |
33585 |
0 |
0 |
T20 |
57686 |
56749 |
0 |
0 |
T25 |
32507 |
31765 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
415561848 |
411109490 |
0 |
0 |
T1 |
203368 |
203097 |
0 |
0 |
T4 |
129165 |
42153 |
0 |
0 |
T5 |
156647 |
156252 |
0 |
0 |
T6 |
1886 |
1723 |
0 |
0 |
T7 |
3304 |
3156 |
0 |
0 |
T17 |
6269 |
6093 |
0 |
0 |
T18 |
5183 |
5021 |
0 |
0 |
T19 |
3377 |
3297 |
0 |
0 |
T20 |
6946 |
6784 |
0 |
0 |
T25 |
2402 |
2335 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
415561848 |
411102428 |
0 |
2415 |
T1 |
203368 |
203094 |
0 |
3 |
T4 |
129165 |
42102 |
0 |
3 |
T5 |
156647 |
156243 |
0 |
3 |
T6 |
1886 |
1720 |
0 |
3 |
T7 |
3304 |
3153 |
0 |
3 |
T17 |
6269 |
6090 |
0 |
3 |
T18 |
5183 |
5018 |
0 |
3 |
T19 |
3377 |
3294 |
0 |
3 |
T20 |
6946 |
6781 |
0 |
3 |
T25 |
2402 |
2332 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
415561848 |
27955 |
0 |
0 |
T1 |
203368 |
0 |
0 |
0 |
T2 |
0 |
310 |
0 |
0 |
T3 |
0 |
448 |
0 |
0 |
T4 |
129165 |
0 |
0 |
0 |
T5 |
156647 |
23 |
0 |
0 |
T6 |
1886 |
0 |
0 |
0 |
T7 |
3304 |
35 |
0 |
0 |
T17 |
6269 |
0 |
0 |
0 |
T18 |
5183 |
0 |
0 |
0 |
T19 |
3377 |
0 |
0 |
0 |
T20 |
6946 |
0 |
0 |
0 |
T21 |
0 |
14 |
0 |
0 |
T22 |
0 |
36 |
0 |
0 |
T25 |
2402 |
55 |
0 |
0 |
T29 |
0 |
32 |
0 |
0 |
T30 |
0 |
43 |
0 |
0 |
T46 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160990400 |
0 |
2415 |
T1 |
205499 |
205222 |
0 |
3 |
T4 |
26910 |
8731 |
0 |
3 |
T5 |
37628 |
37553 |
0 |
3 |
T6 |
1054 |
967 |
0 |
3 |
T7 |
1720 |
1640 |
0 |
3 |
T17 |
1566 |
1520 |
0 |
3 |
T18 |
1349 |
1304 |
0 |
3 |
T19 |
1512 |
1473 |
0 |
3 |
T20 |
1017 |
992 |
0 |
3 |
T25 |
2427 |
2357 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
17202 |
0 |
0 |
T1 |
205499 |
0 |
0 |
0 |
T2 |
0 |
187 |
0 |
0 |
T3 |
0 |
318 |
0 |
0 |
T4 |
26910 |
0 |
0 |
0 |
T5 |
37628 |
15 |
0 |
0 |
T6 |
1054 |
0 |
0 |
0 |
T7 |
1720 |
25 |
0 |
0 |
T17 |
1566 |
0 |
0 |
0 |
T18 |
1349 |
0 |
0 |
0 |
T19 |
1512 |
0 |
0 |
0 |
T20 |
1017 |
0 |
0 |
0 |
T22 |
0 |
24 |
0 |
0 |
T25 |
2427 |
4 |
0 |
0 |
T29 |
0 |
11 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T32 |
0 |
14 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T7,T25 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T25 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160990400 |
0 |
2415 |
T1 |
205499 |
205222 |
0 |
3 |
T4 |
26910 |
8731 |
0 |
3 |
T5 |
37628 |
37553 |
0 |
3 |
T6 |
1054 |
967 |
0 |
3 |
T7 |
1720 |
1640 |
0 |
3 |
T17 |
1566 |
1520 |
0 |
3 |
T18 |
1349 |
1304 |
0 |
3 |
T19 |
1512 |
1473 |
0 |
3 |
T20 |
1017 |
992 |
0 |
3 |
T25 |
2427 |
2357 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
19742 |
0 |
0 |
T1 |
205499 |
0 |
0 |
0 |
T2 |
0 |
216 |
0 |
0 |
T3 |
0 |
333 |
0 |
0 |
T4 |
26910 |
0 |
0 |
0 |
T5 |
37628 |
7 |
0 |
0 |
T6 |
1054 |
0 |
0 |
0 |
T7 |
1720 |
19 |
0 |
0 |
T17 |
1566 |
0 |
0 |
0 |
T18 |
1349 |
0 |
0 |
0 |
T19 |
1512 |
0 |
0 |
0 |
T20 |
1017 |
0 |
0 |
0 |
T21 |
0 |
12 |
0 |
0 |
T22 |
0 |
32 |
0 |
0 |
T25 |
2427 |
45 |
0 |
0 |
T29 |
0 |
18 |
0 |
0 |
T30 |
0 |
35 |
0 |
0 |
T46 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
440689366 |
0 |
0 |
T1 |
211849 |
211709 |
0 |
0 |
T4 |
134553 |
89526 |
0 |
0 |
T5 |
229179 |
228939 |
0 |
0 |
T6 |
1784 |
1644 |
0 |
0 |
T7 |
3442 |
3373 |
0 |
0 |
T17 |
6530 |
6446 |
0 |
0 |
T18 |
5399 |
5287 |
0 |
0 |
T19 |
3518 |
3478 |
0 |
0 |
T20 |
7212 |
7158 |
0 |
0 |
T25 |
2502 |
2476 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
440689366 |
0 |
0 |
T1 |
211849 |
211709 |
0 |
0 |
T4 |
134553 |
89526 |
0 |
0 |
T5 |
229179 |
228939 |
0 |
0 |
T6 |
1784 |
1644 |
0 |
0 |
T7 |
3442 |
3373 |
0 |
0 |
T17 |
6530 |
6446 |
0 |
0 |
T18 |
5399 |
5287 |
0 |
0 |
T19 |
3518 |
3478 |
0 |
0 |
T20 |
7212 |
7158 |
0 |
0 |
T25 |
2502 |
2476 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
415561848 |
413317390 |
0 |
0 |
T1 |
203368 |
203234 |
0 |
0 |
T4 |
129165 |
85940 |
0 |
0 |
T5 |
156647 |
156416 |
0 |
0 |
T6 |
1886 |
1751 |
0 |
0 |
T7 |
3304 |
3238 |
0 |
0 |
T17 |
6269 |
6189 |
0 |
0 |
T18 |
5183 |
5076 |
0 |
0 |
T19 |
3377 |
3338 |
0 |
0 |
T20 |
6946 |
6893 |
0 |
0 |
T25 |
2402 |
2377 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
415561848 |
413317390 |
0 |
0 |
T1 |
203368 |
203234 |
0 |
0 |
T4 |
129165 |
85940 |
0 |
0 |
T5 |
156647 |
156416 |
0 |
0 |
T6 |
1886 |
1751 |
0 |
0 |
T7 |
3304 |
3238 |
0 |
0 |
T17 |
6269 |
6189 |
0 |
0 |
T18 |
5183 |
5076 |
0 |
0 |
T19 |
3377 |
3338 |
0 |
0 |
T20 |
6946 |
6893 |
0 |
0 |
T25 |
2402 |
2377 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206936213 |
206936213 |
0 |
0 |
T1 |
101617 |
101617 |
0 |
0 |
T4 |
42975 |
42975 |
0 |
0 |
T5 |
78406 |
78406 |
0 |
0 |
T6 |
876 |
876 |
0 |
0 |
T7 |
1771 |
1771 |
0 |
0 |
T17 |
3095 |
3095 |
0 |
0 |
T18 |
2538 |
2538 |
0 |
0 |
T19 |
1669 |
1669 |
0 |
0 |
T20 |
3447 |
3447 |
0 |
0 |
T25 |
1222 |
1222 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206936213 |
206936213 |
0 |
0 |
T1 |
101617 |
101617 |
0 |
0 |
T4 |
42975 |
42975 |
0 |
0 |
T5 |
78406 |
78406 |
0 |
0 |
T6 |
876 |
876 |
0 |
0 |
T7 |
1771 |
1771 |
0 |
0 |
T17 |
3095 |
3095 |
0 |
0 |
T18 |
2538 |
2538 |
0 |
0 |
T19 |
1669 |
1669 |
0 |
0 |
T20 |
3447 |
3447 |
0 |
0 |
T25 |
1222 |
1222 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
103467486 |
103467486 |
0 |
0 |
T1 |
50809 |
50809 |
0 |
0 |
T4 |
21486 |
21486 |
0 |
0 |
T5 |
39202 |
39202 |
0 |
0 |
T6 |
438 |
438 |
0 |
0 |
T7 |
885 |
885 |
0 |
0 |
T17 |
1547 |
1547 |
0 |
0 |
T18 |
1269 |
1269 |
0 |
0 |
T19 |
835 |
835 |
0 |
0 |
T20 |
1723 |
1723 |
0 |
0 |
T25 |
610 |
610 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
103467486 |
103467486 |
0 |
0 |
T1 |
50809 |
50809 |
0 |
0 |
T4 |
21486 |
21486 |
0 |
0 |
T5 |
39202 |
39202 |
0 |
0 |
T6 |
438 |
438 |
0 |
0 |
T7 |
885 |
885 |
0 |
0 |
T17 |
1547 |
1547 |
0 |
0 |
T18 |
1269 |
1269 |
0 |
0 |
T19 |
835 |
835 |
0 |
0 |
T20 |
1723 |
1723 |
0 |
0 |
T25 |
610 |
610 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
212569675 |
211441736 |
0 |
0 |
T1 |
101689 |
101622 |
0 |
0 |
T4 |
64585 |
42973 |
0 |
0 |
T5 |
110007 |
109891 |
0 |
0 |
T6 |
944 |
877 |
0 |
0 |
T7 |
1652 |
1619 |
0 |
0 |
T17 |
3134 |
3094 |
0 |
0 |
T18 |
2592 |
2538 |
0 |
0 |
T19 |
1688 |
1669 |
0 |
0 |
T20 |
3408 |
3382 |
0 |
0 |
T25 |
1201 |
1188 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
212569675 |
211441736 |
0 |
0 |
T1 |
101689 |
101622 |
0 |
0 |
T4 |
64585 |
42973 |
0 |
0 |
T5 |
110007 |
109891 |
0 |
0 |
T6 |
944 |
877 |
0 |
0 |
T7 |
1652 |
1619 |
0 |
0 |
T17 |
3134 |
3094 |
0 |
0 |
T18 |
2592 |
2538 |
0 |
0 |
T19 |
1688 |
1669 |
0 |
0 |
T20 |
3408 |
3382 |
0 |
0 |
T25 |
1201 |
1188 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160990400 |
0 |
2415 |
T1 |
205499 |
205222 |
0 |
3 |
T4 |
26910 |
8731 |
0 |
3 |
T5 |
37628 |
37553 |
0 |
3 |
T6 |
1054 |
967 |
0 |
3 |
T7 |
1720 |
1640 |
0 |
3 |
T17 |
1566 |
1520 |
0 |
3 |
T18 |
1349 |
1304 |
0 |
3 |
T19 |
1512 |
1473 |
0 |
3 |
T20 |
1017 |
992 |
0 |
3 |
T25 |
2427 |
2357 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160990400 |
0 |
2415 |
T1 |
205499 |
205222 |
0 |
3 |
T4 |
26910 |
8731 |
0 |
3 |
T5 |
37628 |
37553 |
0 |
3 |
T6 |
1054 |
967 |
0 |
3 |
T7 |
1720 |
1640 |
0 |
3 |
T17 |
1566 |
1520 |
0 |
3 |
T18 |
1349 |
1304 |
0 |
3 |
T19 |
1512 |
1473 |
0 |
3 |
T20 |
1017 |
992 |
0 |
3 |
T25 |
2427 |
2357 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160990400 |
0 |
2415 |
T1 |
205499 |
205222 |
0 |
3 |
T4 |
26910 |
8731 |
0 |
3 |
T5 |
37628 |
37553 |
0 |
3 |
T6 |
1054 |
967 |
0 |
3 |
T7 |
1720 |
1640 |
0 |
3 |
T17 |
1566 |
1520 |
0 |
3 |
T18 |
1349 |
1304 |
0 |
3 |
T19 |
1512 |
1473 |
0 |
3 |
T20 |
1017 |
992 |
0 |
3 |
T25 |
2427 |
2357 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160990400 |
0 |
2415 |
T1 |
205499 |
205222 |
0 |
3 |
T4 |
26910 |
8731 |
0 |
3 |
T5 |
37628 |
37553 |
0 |
3 |
T6 |
1054 |
967 |
0 |
3 |
T7 |
1720 |
1640 |
0 |
3 |
T17 |
1566 |
1520 |
0 |
3 |
T18 |
1349 |
1304 |
0 |
3 |
T19 |
1512 |
1473 |
0 |
3 |
T20 |
1017 |
992 |
0 |
3 |
T25 |
2427 |
2357 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160990400 |
0 |
2415 |
T1 |
205499 |
205222 |
0 |
3 |
T4 |
26910 |
8731 |
0 |
3 |
T5 |
37628 |
37553 |
0 |
3 |
T6 |
1054 |
967 |
0 |
3 |
T7 |
1720 |
1640 |
0 |
3 |
T17 |
1566 |
1520 |
0 |
3 |
T18 |
1349 |
1304 |
0 |
3 |
T19 |
1512 |
1473 |
0 |
3 |
T20 |
1017 |
992 |
0 |
3 |
T25 |
2427 |
2357 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160990400 |
0 |
2415 |
T1 |
205499 |
205222 |
0 |
3 |
T4 |
26910 |
8731 |
0 |
3 |
T5 |
37628 |
37553 |
0 |
3 |
T6 |
1054 |
967 |
0 |
3 |
T7 |
1720 |
1640 |
0 |
3 |
T17 |
1566 |
1520 |
0 |
3 |
T18 |
1349 |
1304 |
0 |
3 |
T19 |
1512 |
1473 |
0 |
3 |
T20 |
1017 |
992 |
0 |
3 |
T25 |
2427 |
2357 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163702864 |
160997641 |
0 |
0 |
T1 |
205499 |
205225 |
0 |
0 |
T4 |
26910 |
8798 |
0 |
0 |
T5 |
37628 |
37562 |
0 |
0 |
T6 |
1054 |
970 |
0 |
0 |
T7 |
1720 |
1643 |
0 |
0 |
T17 |
1566 |
1523 |
0 |
0 |
T18 |
1349 |
1307 |
0 |
0 |
T19 |
1512 |
1476 |
0 |
0 |
T20 |
1017 |
995 |
0 |
0 |
T25 |
2427 |
2360 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438357416 |
0 |
2415 |
T1 |
211849 |
211563 |
0 |
3 |
T4 |
134553 |
43861 |
0 |
3 |
T5 |
229179 |
228757 |
0 |
3 |
T6 |
1784 |
1612 |
0 |
3 |
T7 |
3442 |
3284 |
0 |
3 |
T17 |
6530 |
6343 |
0 |
3 |
T18 |
5399 |
5227 |
0 |
3 |
T19 |
3518 |
3432 |
0 |
3 |
T20 |
7212 |
7041 |
0 |
3 |
T25 |
2502 |
2430 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
31904 |
0 |
0 |
T1 |
211849 |
1 |
0 |
0 |
T4 |
134553 |
17 |
0 |
0 |
T5 |
229179 |
19 |
0 |
0 |
T6 |
1784 |
8 |
0 |
0 |
T7 |
3442 |
8 |
0 |
0 |
T17 |
6530 |
3 |
0 |
0 |
T18 |
5399 |
16 |
0 |
0 |
T19 |
3518 |
3 |
0 |
0 |
T20 |
7212 |
17 |
0 |
0 |
T25 |
2502 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438357416 |
0 |
2415 |
T1 |
211849 |
211563 |
0 |
3 |
T4 |
134553 |
43861 |
0 |
3 |
T5 |
229179 |
228757 |
0 |
3 |
T6 |
1784 |
1612 |
0 |
3 |
T7 |
3442 |
3284 |
0 |
3 |
T17 |
6530 |
6343 |
0 |
3 |
T18 |
5399 |
5227 |
0 |
3 |
T19 |
3518 |
3432 |
0 |
3 |
T20 |
7212 |
7041 |
0 |
3 |
T25 |
2502 |
2430 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
31880 |
0 |
0 |
T1 |
211849 |
1 |
0 |
0 |
T4 |
134553 |
17 |
0 |
0 |
T5 |
229179 |
29 |
0 |
0 |
T6 |
1784 |
4 |
0 |
0 |
T7 |
3442 |
8 |
0 |
0 |
T17 |
6530 |
3 |
0 |
0 |
T18 |
5399 |
16 |
0 |
0 |
T19 |
3518 |
3 |
0 |
0 |
T20 |
7212 |
9 |
0 |
0 |
T25 |
2502 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438357416 |
0 |
2415 |
T1 |
211849 |
211563 |
0 |
3 |
T4 |
134553 |
43861 |
0 |
3 |
T5 |
229179 |
228757 |
0 |
3 |
T6 |
1784 |
1612 |
0 |
3 |
T7 |
3442 |
3284 |
0 |
3 |
T17 |
6530 |
6343 |
0 |
3 |
T18 |
5399 |
5227 |
0 |
3 |
T19 |
3518 |
3432 |
0 |
3 |
T20 |
7212 |
7041 |
0 |
3 |
T25 |
2502 |
2430 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
32001 |
0 |
0 |
T1 |
211849 |
1 |
0 |
0 |
T4 |
134553 |
17 |
0 |
0 |
T5 |
229179 |
33 |
0 |
0 |
T6 |
1784 |
4 |
0 |
0 |
T7 |
3442 |
10 |
0 |
0 |
T17 |
6530 |
3 |
0 |
0 |
T18 |
5399 |
17 |
0 |
0 |
T19 |
3518 |
3 |
0 |
0 |
T20 |
7212 |
5 |
0 |
0 |
T25 |
2502 |
22 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438357416 |
0 |
2415 |
T1 |
211849 |
211563 |
0 |
3 |
T4 |
134553 |
43861 |
0 |
3 |
T5 |
229179 |
228757 |
0 |
3 |
T6 |
1784 |
1612 |
0 |
3 |
T7 |
3442 |
3284 |
0 |
3 |
T17 |
6530 |
6343 |
0 |
3 |
T18 |
5399 |
5227 |
0 |
3 |
T19 |
3518 |
3432 |
0 |
3 |
T20 |
7212 |
7041 |
0 |
3 |
T25 |
2502 |
2430 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
31787 |
0 |
0 |
T1 |
211849 |
1 |
0 |
0 |
T4 |
134553 |
17 |
0 |
0 |
T5 |
229179 |
25 |
0 |
0 |
T6 |
1784 |
5 |
0 |
0 |
T7 |
3442 |
10 |
0 |
0 |
T17 |
6530 |
3 |
0 |
0 |
T18 |
5399 |
14 |
0 |
0 |
T19 |
3518 |
3 |
0 |
0 |
T20 |
7212 |
9 |
0 |
0 |
T25 |
2502 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443046840 |
438364558 |
0 |
0 |
T1 |
211849 |
211566 |
0 |
0 |
T4 |
134553 |
43912 |
0 |
0 |
T5 |
229179 |
228766 |
0 |
0 |
T6 |
1784 |
1615 |
0 |
0 |
T7 |
3442 |
3287 |
0 |
0 |
T17 |
6530 |
6346 |
0 |
0 |
T18 |
5399 |
5230 |
0 |
0 |
T19 |
3518 |
3435 |
0 |
0 |
T20 |
7212 |
7044 |
0 |
0 |
T25 |
2502 |
2433 |
0 |
0 |