Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T4,T46

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	163702864	160856947	0	0
AllClkBypReqTrue_A	163702864	138340	0	0
IoClkBypReqFalse_A	163702864	160775910	0	2415
IoClkBypReqTrue_A	163702864	214669	0	0
LcClkBypAckFalse_A	163702864	160868459	0	0
LcClkBypAckTrue_A	163702864	126828	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	160856947	0	0
T1	205499	205224	0	0
T4	26910	8781	0	0
T5	37628	37545	0	0
T6	1054	969	0	0
T7	1720	1478	0	0
T17	1566	1522	0	0
T18	1349	1306	0	0
T19	1512	1475	0	0
T20	1017	994	0	0
T25	2427	2220	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	138340	0	0
T1	205499	0	0	0
T2	0	1129	0	0
T3	0	4905	0	0
T4	26910	0	0	0
T5	37628	14	0	0
T6	1054	0	0	0
T7	1720	164	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T21	0	4	0	0
T22	0	253	0	0
T25	2427	139	0	0
T29	0	122	0	0
T30	0	165	0	0
T46	0	84	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	160775910	0	2415
T1	205499	205222	0	3
T4	26910	8747	0	3
T5	37628	37431	0	3
T6	1054	967	0	3
T7	1720	1359	0	3
T17	1566	1520	0	3
T18	1349	1304	0	3
T19	1512	1473	0	3
T20	1017	992	0	3
T25	2427	2312	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	214669	0	0
T1	205499	0	0	0
T2	0	1795	0	0
T3	0	6171	0	0
T4	26910	0	0	0
T5	37628	122	0	0
T6	1054	0	0	0
T7	1720	281	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T22	0	322	0	0
T25	2427	45	0	0
T29	0	151	0	0
T30	0	54	0	0
T32	0	136	0	0
T46	0	93	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	160868459	0	0
T1	205499	205224	0	0
T4	26910	8781	0	0
T5	37628	37514	0	0
T6	1054	969	0	0
T7	1720	1490	0	0
T17	1566	1522	0	0
T18	1349	1306	0	0
T19	1512	1475	0	0
T20	1017	994	0	0
T25	2427	2359	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	126828	0	0
T1	205499	0	0	0
T2	0	1163	0	0
T3	0	4179	0	0
T4	26910	0	0	0
T5	37628	45	0	0
T6	1054	0	0	0
T7	1720	152	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T22	0	255	0	0
T25	2427	0	0	0
T29	0	101	0	0
T32	0	36	0	0
T39	0	191	0	0
T46	0	55	0	0
T108	0	305	0	0