Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1772189096	15224	0	0
TransStop_A	1772189096	7854	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1772189096	15224	0	0
T1	847396	0	0	0
T2	0	258	0	0
T3	0	327	0	0
T4	538212	0	0	0
T5	916716	4	0	0
T6	7136	0	0	0
T7	13768	0	0	0
T17	26120	0	0	0
T18	21600	10	0	0
T19	14072	4	0	0
T20	28852	0	0	0
T24	0	17	0	0
T25	10008	0	0	0
T38	0	17	0	0
T46	0	30	0	0
T109	0	28	0	0
T110	0	22	0	0
T111	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1772189096	7854	0	0
T2	2291524	132	0	0
T3	0	163	0	0
T4	538212	0	0	0
T18	16200	4	0	0
T19	14072	4	0	0
T20	28852	0	0	0
T21	28212	0	0	0
T22	28140	0	0	0
T23	250588	0	0	0
T24	100696	11	0	0
T28	2820	0	0	0
T38	0	9	0	0
T46	113364	19	0	0
T109	0	13	0	0
T110	0	16	0	0
T111	0	10	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	443047274	3816	0	0
TransStop_A	443047274	1984	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443047274	3816	0	0
T1	211849	0	0	0
T2	0	66	0	0
T3	0	88	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	0	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5400	3	0	0
T19	3518	1	0	0
T20	7213	0	0	0
T24	0	7	0	0
T25	2502	0	0	0
T38	0	4	0	0
T46	0	8	0	0
T109	0	4	0	0
T110	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443047274	1984	0	0
T2	572881	33	0	0
T3	0	44	0	0
T4	134553	0	0	0
T18	5400	1	0	0
T19	3518	1	0	0
T20	7213	0	0	0
T21	7053	0	0	0
T22	7035	0	0	0
T23	62647	0	0	0
T24	25174	5	0	0
T38	0	3	0	0
T46	28341	5	0	0
T109	0	3	0	0
T110	0	5	0	0
T111	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	443047274	3811	0	0
TransStop_A	443047274	1957	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443047274	3811	0	0
T1	211849	0	0	0
T2	0	59	0	0
T3	0	84	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	0	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5400	0	0	0
T19	3518	1	0	0
T20	7213	0	0	0
T24	0	2	0	0
T25	2502	0	0	0
T38	0	5	0	0
T46	0	6	0	0
T109	0	9	0	0
T110	0	5	0	0
T111	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443047274	1957	0	0
T2	572881	32	0	0
T3	0	44	0	0
T4	134553	0	0	0
T19	3518	1	0	0
T20	7213	0	0	0
T21	7053	0	0	0
T22	7035	0	0	0
T23	62647	0	0	0
T24	25174	2	0	0
T28	2820	0	0	0
T38	0	4	0	0
T46	28341	4	0	0
T109	0	4	0	0
T110	0	3	0	0
T111	0	2	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	443047274	3857	0	0
TransStop_A	443047274	1982	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443047274	3857	0	0
T1	211849	0	0	0
T2	0	65	0	0
T3	0	73	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	0	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5400	3	0	0
T19	3518	1	0	0
T20	7213	0	0	0
T24	0	2	0	0
T25	2502	0	0	0
T38	0	5	0	0
T46	0	8	0	0
T109	0	5	0	0
T110	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443047274	1982	0	0
T2	572881	33	0	0
T3	0	32	0	0
T4	134553	0	0	0
T18	5400	1	0	0
T19	3518	1	0	0
T20	7213	0	0	0
T21	7053	0	0	0
T22	7035	0	0	0
T23	62647	0	0	0
T24	25174	2	0	0
T38	0	1	0	0
T46	28341	5	0	0
T109	0	2	0	0
T110	0	3	0	0
T111	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	443047274	3740	0	0
TransStop_A	443047274	1931	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443047274	3740	0	0
T1	211849	0	0	0
T2	0	68	0	0
T3	0	82	0	0
T4	134553	0	0	0
T5	229179	1	0	0
T6	1784	0	0	0
T7	3442	0	0	0
T17	6530	0	0	0
T18	5400	4	0	0
T19	3518	1	0	0
T20	7213	0	0	0
T24	0	6	0	0
T25	2502	0	0	0
T38	0	3	0	0
T46	0	8	0	0
T109	0	10	0	0
T110	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443047274	1931	0	0
T2	572881	34	0	0
T3	0	43	0	0
T4	134553	0	0	0
T18	5400	2	0	0
T19	3518	1	0	0
T20	7213	0	0	0
T21	7053	0	0	0
T22	7035	0	0	0
T23	62647	0	0	0
T24	25174	2	0	0
T38	0	1	0	0
T46	28341	5	0	0
T109	0	4	0	0
T110	0	5	0	0
T111	0	2	0	0