Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	163702864	26436426	0	55

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163702864	26436426	0	55
T1	205499	59392	0	1
T2	0	229063	0	0
T3	0	705149	0	0
T4	26910	0	0	0
T10	0	6911	0	1
T11	0	35625	0	1
T12	0	827324	0	0
T13	0	17443	0	0
T14	0	472461	0	0
T15	0	18933	0	1
T16	0	229001	0	0
T17	1566	0	0	0
T18	1349	0	0	0
T19	1512	0	0	0
T20	1017	0	0	0
T21	1057	0	0	0
T22	1687	0	0	0
T23	30697	0	0	0
T24	1762	0	0	0
T37	0	0	0	1
T40	0	0	0	1
T63	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1
T115	0	0	0	1